Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

which fpga language is widely used

Status
Not open for further replies.
E

ep.hobbyiest

Full Member level 4
Joined
Jul 24, 2014
Messages
212
Helped
1
Reputation
2
Reaction score
1
Trophy points
18
Activity points
1,487
i am new to fpga.i am confuse in deciding which language is to select. VHDL or Verilog. i read about this on google. but i need advise.
 

You can write verilog to look like VHDL.

VHDL has a stronghold on security an CV. Verilog on ASICs.

For features, it is really SystemVerilog vs VHDL2008.
 

vGoodtimes said:
For features, it is really SystemVerilog vs VHDL2008.
Click to expand...

But then neither of them adds anything groundbreaking to the basic Verilog or VHDL 93 for synthesis (well maybe the fixed_pkg, but good luck getting support for the proper version any time soon).

Support has been quite poor from the main vendor tools, especially with VHDL 2008. Xilinx actually now has better 2008 support than Altera (which I thought would never happen!). And SV support is/was much better in Quartus.

SV and VHDL2008 add much more in the verification space which is well supported by the sim tools.

People have been talking about the death of VHDL for years. It is still here. We'll have to see where it goes. Altera are now developing their IP in SV.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top