which fpga language is widely used

[ep.hobbyiest]

i am new to fpga.i am confuse in deciding which language is to select. VHDL or Verilog. i read about this on google. but i need advise.

 

[vGoodtimes]

You can write verilog to look like VHDL.

VHDL has a stronghold on security an CV. Verilog on ASICs.

For features, it is really SystemVerilog vs VHDL2008.

 

[TrickyDicky]

For features, it is really SystemVerilog vs VHDL2008.

But then neither of them adds anything groundbreaking to the basic Verilog or VHDL 93 for synthesis (well maybe the fixed_pkg, but good luck getting support for the proper version any time soon).

Support has been quite poor from the main vendor tools, especially with VHDL 2008. Xilinx actually now has better 2008 support than Altera (which I thought would never happen!). And SV support is/was much better in Quartus.

SV and VHDL2008 add much more in the verification space which is well supported by the sim tools.

People have been talking about the death of VHDL for years. It is still here. We'll have to see where it goes. Altera are now developing their IP in SV.