Implementing 32-bit multiplier at the gate-level

Hey all,

I was wondering if you could help me with my homework.
I need to implement a 4-bit multiplier at the gate-level in verilog using AND gates and adders

I've drawn the layout, but I'm having trouble translating it to Verilog.

When I instantiate an AND-gate, how do I extract the least significant bit from the AND's output?

for instance, I instantiate an AND gate like so:
// multiplicand = 4'b1011, multiplier = 4'b1110

and(result, multiplicand, {4{multiplier[0]}});

Mathematically, this would be 1011 & 0000 = 0000 <- result
How would I extract the least significant bit at the 0th index and store it at at p[1] or low[1]?

Here's my code, am I on the right track?


Thank you for the help!

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I'm implementing a 4 bit multiplier, but the assignment is to make a 32-bit multiplier. I'm doing it on a small scale to make sure it works before implementing the full 32 bits.

Here's the gate design

Yes. You need to use assign.

Yes, you are on the right track.

See this link for some info on assign statements and always blocks : https://www.asic-world.com/verilog/verilog_one_day3.html

and(and_result[0], mcnd, {4{mplr[0]}});
is not the correct way to instantiate the Verilog and gate primitive.

and and_instance_name (and_out, and_a_in, and_b_in);
The Verilog and primitive has one single bit output and multiple single bit inputs.

to implement this as you are trying to do:
and and_instance_name [3:0] (and_result[0], mcnd, {4{mplr[0]}});

this creates 4 and_instance_name instances, 1 for each output bit of the and_result signal.

ads-ee said:

and(and_result[0], mcnd, {4{mplr[0]}});
is not the correct way to instantiate the Verilog and gate primitive.

and and_instance_name (and_out, and_a_in, and_b_in);
The Verilog and primitive has one single bit output and multiple single bit inputs.

to implement this as you are trying to do:
and and_instance_name [3:0] (and_result[0], mcnd, {4{mplr[0]}});

this creates 4 and_instance_name instances, 1 for each output bit of the and_result signal.

Click to expand...

You were extremely helpful. Thank you so much