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Hi, i have designed a LNA using cadence 0.13um cmos technology with bandwidth of 4-6 GHz. My dc and sp simulation run well but my pss simulation keep terminating and show me there is an error. Can anyone please help? I have attached the related images
here.
maybe you have some convergence problems sometimes are explained in the log .don't you.
check your circuits connections carefully and your pss analysis parameters and the tones you've given before.
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