Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Have you included model files for the MOSFETs while firing a simulation. If there is no model file then the simulator cannot detect the devices when it reads the netlist file and throws fatal error.
I have model libraries of CMOS 65nm technology but when I am designing individual symbols and cascading of those symbols.It shows fatal error.Is it possible to do cascading?
Have you included model files for the MOSFETs while firing a simulation. If there is no model file then the simulator cannot detect the devices when it reads the netlist file and throws fatal error.
While running a simulation you need two files (1) netlist file which contains the device and there interconnection information (2) The test-bench file which contains the type of simulation (ac , dc, transient) that you want to run on that netlist. Now the test-bench file must have include statements for including the model files and including the netlist. Check whether your test-bench file has include statements for the model file or not.
If possible please attach the two files testbench and netist...
There should not be any problem in cascading .... simulator does not through error on how many stages you add i.e independent of the complexity of the circuit...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
