problem occur during simulation of op-amp on cadence virtuoso

[abhilashkumar]

problem occur during simulation,please help me to remove fatal error during simulation.

 

[SIDDHARTHA HAZRA]

Have you included model files for the MOSFETs while firing a simulation. If there is no model file then the simulator cannot detect the devices when it reads the netlist file and throws fatal error.

 

[abhilashkumar]

I have model libraries of CMOS 65nm technology but when I am designing individual symbols and cascading of those symbols.It shows fatal error.Is it possible to do cascading?

Have you included model files for the MOSFETs while firing a simulation. If there is no model file then the simulator cannot detect the devices when it reads the netlist file and throws fatal error.

 

[SIDDHARTHA HAZRA]

I have model libraries of CMOS 65nm technology

While running a simulation you need two files (1) netlist file which contains the device and there interconnection information (2) The test-bench file which contains the type of simulation (ac , dc, transient) that you want to run on that netlist. Now the test-bench file must have include statements for including the model files and including the netlist. Check whether your test-bench file has include statements for the model file or not.

If possible please attach the two files testbench and netist...

It shows fatal error.Is it possible to do cascading?

There should not be any problem in cascading .... simulator does not through error on how many stages you add i.e independent of the complexity of the circuit...

 

[dick_freebird]

"Having" the data, and Spectre having any idea where
you put it, are two different things.