yupina-chan
Member level 2
hi. can i instantiate a module inside an always block?
what i want to do is save values to a line buffer. i only want to execute my line buffer only at a certain period of time so inside my always block(at positive clock edge the values enter), i have a counter. whenever the counter reaches the specified count, it performs the line buffer module. how can i make this in verilog? thanks in advance
what i want to do is save values to a line buffer. i only want to execute my line buffer only at a certain period of time so inside my always block(at positive clock edge the values enter), i have a counter. whenever the counter reaches the specified count, it performs the line buffer module. how can i make this in verilog? thanks in advance