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questions about timing arc

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honeyxyb

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negative_unate

Hi ,all:
I have some question about library timing arc:

1. what is the different between timing_type and timing_sense?
2. how to understand negative_unate ?
3. in normal case , use rising_edge or falling_edge to specify sequencial logic,
but can I use rising_edge/falling_edge to specify combinatial logic?
If not, why Pathmill generate one library which inverter is descripted using
timing_type with rising_edge and falling_edge?
4. my DFF is not double edge triggle DFF, why pathmill descript it use both
rising_edge and falling_edge?
 

timing arc

negative_unate : such as Inverter, output transition is the opposite of input transisiton
buffer is kind of positive_unate.
 

positive_unate

timing_type is rising or falling_edge
timing_sense is positive_unate or negtive_unate
 

timing arcs

Can someone provide detail example to explain this timing problem ?
 

arc timing

3.for combinational logic , the falling/rising edge mean the signal transition on endpoint of the path.
 

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