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[SOLVED] Wire/net delay reporting in PrimeTime

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soloktanjung

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Hi,

I want to know how much wire/net delay contribute in my critical paths, so I use report_timing -nets command in PrimeTime but there is no value for each net as shown below. Does anyone know how to know the exact net delay?

Thanks in advance.

Code: 
  Point                                                                Fanout    Cap      Trans       Incr       Path
--------------------------------------------------------------------------------------------------------------------------------------------------
  clock network delay (ideal)                                                                                      1.00       1.00
  input external delay                                                                                                0.50       1.50 r
  rst_i (in)                                                                                                   0.05       0.02 &     1.52 r
  rst_i (net)                                                                         1     0.01 
  FE_OFC2540_rst_i/Z (HS45_LS_IVX35)                                                     0.02       0.04 &     1.56 f
[B]  FE_OFN2540_rst_i (net)                                                    2     0.01 
[/B]  FE_OFN2540_rst_i__L1_I0/Z (HS45_LS_CNBFX59)                                   0.02       0.05 &     1.61 f
[B]  FE_OFN2540_rst_i__L1_N0 (net)                                        2     0.01 
[/B]  FE_OFN2540_rst_i__L2_I0/Z (HS45_LS_CNBFX59)                                    0.02       0.05 &     1.65 f
[B]  FE_OFN2540_rst_i__L2_N0 (net)                                        1     0.00 
[/B]  FE_OFN2540_rst_i__L3_I0/Z (HS45_LS_CNBFX59)                                    0.02       0.04 &     1.70 f
  FE_OFN2540_rst_i__L3_N0 (net)                                        1     0.00 
  FE_OFN2540_rst_i__L4_I0/Z (HS45_LS_CNBFX59)                                    0.02       0.05 &     1.74 f
  FE_OFN2540_rst_i__L4_N0 (net)                                        1     0.00 
  FE_OFN2540_rst_i__L5_I0/Z (HS45_LS_CNBFX59)                                    0.02       0.04 &     1.79 f
  FE_OFN2540_rst_i__L5_N0 (net)                                        1     0.00 
  FE_OFN2540_rst_i__L6_I0/Z (HS45_LS_CNBFX59)                                    0.02       0.04 &     1.83 f
 

Sorry For last post..

Please find the ans..

The option -nets displays the net name and its associated fanout. To see net
delay, use the option -input_pins. This displays the net delay (displayed at
the input pin) and the cell delay (displayed at the output pin). You may also
want to increase the number of significant digits with the -significant_digits
option.

report_timing -nets -input_pins -significant_digits 3
 
Last edited:
Thanks for the quick response. But I do not see any delay values for nets. Below is the output of report_timing -nets -input-pins -significants_digits 3 command:


Code: 
  Point                                                 Fanout       Incr       Path
  -------------------------------------------------------------------------
  clock clk_noc_i_v (rise edge)                                          0.000      0.000
  clock network delay (ideal)                                             1.000      1.000
  input external delay                                                      0.500      1.500 r
  rst_i (in)                                                                    0.020 &    1.520 r
[B]  rst_i (net)                                                       1 
[/B]  FE_OFC2540_rst_i/A (HS45_LS_IVX35)                            0.000 &    1.520 r
  FE_OFC2540_rst_i/Z (HS45_LS_IVX35)                            0.035 &    1.555 f
[B]  FE_OFN2540_rst_i (net)                                     2 
[/B]  FE_OFN2540_rst_i__L1_I0/A (HS45_LS_CNBFX59)              0.000 &    1.556 f
  FE_OFN2540_rst_i__L1_I0/Z (HS45_LS_CNBFX59)              0.050 &    1.605 f
  FE_OFN2540_rst_i__L1_N0 (net)                          2 
  FE_OFN2540_rst_i__L2_I0/A (HS45_LS_CNBFX59)              0.000 &    1.606 f
  FE_OFN2540_rst_i__L2_I0/Z (HS45_LS_CNBFX59)              0.046 &    1.651 f
  FE_OFN2540_rst_i__L2_N0 (net)                          1 
  FE_OFN2540_rst_i__L3_I0/A (HS45_LS_CNBFX59)              0.000 &    1.651 f
  FE_OFN2540_rst_i__L3_I0/Z (HS45_LS_CNBFX59)              0.045 &    1.696 f
  FE_OFN2540_rst_i__L3_N0 (net)                          1 
  FE_OFN2540_rst_i__L4_I0/A (HS45_LS_CNBFX59)              0.000 &    1.696 f
  ...
  ...
  ...
[B]  FE_OCPN2862_FE_OFN2542_rst_i__L4_N0 (net)     1 
[/B]  .../FE_OCPN2862_FE_OFN2542_rst_i__L4_N0 (top_10_10_35_6_4_1_87_6_6_32_4_32_10_32_10_2_32)          0.000 &    2.365 r

How can I differentiate the gate delay with the net delay in that path?

Thanks again.
 
Last edited:

Did you see that your clock network is considered as ideal?
I think you should add the clock propagated inside your sdc, to properly handle the timing.
 

Thanks for the reply. Yes I know the clock is ideal because that is a virtual clock. I am able to see the net delay in the critical path through path histogram in the GUI.

Thank you.
 

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