tfuser
Newbie level 2
My customer design is something like below. Toplevel PAD is also driven by core logic and memory output. The memory output seems to be driven by the PAD1 due to the fact that its connected to PAD1 port by tranif0 (en1 is always on for this case). Does tranif0 overpower even 'output' signals of other blocks ? The reason I see this is its reading back from an address not defined in the input ROM code.
Thanks.
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module top( PAD1, ....);
inout PAD1;
...
tranif0 #(0,0) G02 (PAD1, DAT_7, en1);
block1 BLK1 (PAD1, ....);
rom512x8 MEM1 (.O7(DAT_7), .....);
endmodule
module rom512x8 (O7, ....);
output O7;
...
endmodule
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Thanks.
**********************cut****************
module top( PAD1, ....);
inout PAD1;
...
tranif0 #(0,0) G02 (PAD1, DAT_7, en1);
block1 BLK1 (PAD1, ....);
rom512x8 MEM1 (.O7(DAT_7), .....);
endmodule
module rom512x8 (O7, ....);
output O7;
...
endmodule
**********************cut****************