Synopsys Power compiler issue

Hi, Friends:
I don't want DC to use chip input signals to generate clcok gating enable. How can I achieve this?
Thanks.

When you use the -gate_clock option, clock gating is implemented in the design according to options set by the set_clock_gating_style command.

For clock gating to be applied in your design..you need one of two things
1. Component instantiation or
2. Functional implication

So take care in these two stages that your input signals do not involve...
For example, you can(from userguide)
• Choose an integrated or nonintegrated cell with latch-based clock gating
• Choose an integrated or nonintegrated cell with latch-free clock gating
• Insert logic to increase testability
• Specify a minimum number of bits below which clock gating is not inserted
• Explicitly include signals in clock gating
• Explicitly exclude signals from clock gating
• Specify a maximum number for the fanouts of each clock-gating element
• Move a clock-gated register to another clock-gating cell
• Resize the clock-gating element

By default DC do not make use of your input signals....For more info please refer library compiler user guide.

cheers