+ Post New Thread
Results 1 to 4 of 4
  1. #1
    Junior Member level 1
    Points: 1,681, Level: 9

    Join Date
    Dec 2004
    Posts
    18
    Helped
    0 / 0
    Points
    1,681
    Level
    9

    Vertical PNP ERC error in Calibre:"NWELL Regions should be tied to POWER"

    Hello everyone,

    I am currently designing a bandgap reference (BGR) circuit in IBM cms9flp.

    Using Assura for LVS the circuit is shown to be correct (layout schematic match, and no extraction problems)

    When I use Calibre the result is Correct again, there are no extraction problems, BUT there is an ERC error. The description of the error is:
    ERC2
    All NWELL Regions should be tied to POWER or most positive chip supply. FRom LVS deck, NWELL = NW NOT (N3 OR NWRES OR NW_RES)


    but it points to my vertical pnps (I have taken care to properly bias the nwell all the PMOS in the circuit)

    The base of the vpnp pcell is connected to the nwell. But in BGR circuits the collector and the base are both connected to ground. So, this nwell is connected to ground, and not to a POWER net, and thus, I get the ERC error.

    But I believe there would be no problem in practice, since the collector (that is the substrate) and the base (that is the nwell) are both connected to ground, and thus the parasitic substrate-nwell diode will never get forward biased and conduct current.

    According to this rule, I would get no error only if I connected the base of the vpnp to a POWER net eg VDD, but then the vpnp would be a useless device!! (because Veb would be zero or negative)

    I think that there should be an exception in this rule, when the nwell belongs to a vpnp.

    Has anybody faced this problem again?
    I would appreciate I you shared your view in this issue.

    Thank you very much in advance,
    mixaloybas

    •   Alt29th December 2010, 14:43

      advertising

        
       

  2. #2
    Super Moderator
    Points: 50,804, Level: 55
    Achievements:
    7 years registered
    erikl's Avatar
    Join Date
    Sep 2008
    Location
    Germany
    Posts
    7,993
    Helped
    2596 / 2596
    Points
    50,804
    Level
    55

    Re: Vertical PNP ERC error in Calibre:"NWELL Regions should be tied to POWER"

    Quote Originally Posted by mixaloybas View Post
    I think that there should be an exception in this rule, when the nwell belongs to a vpnp.
    Totally agree.

    I don't have this process lib. But perhaps there exists an "exception" layer, which helps to avoid this dummy error message when applied over the device? I'd suggest to try and find it in the C@libre ERC (or, possibly, in the XTR) rules' set - search for your vpnp model name.


    1 members found this post helpful.

    •   Alt29th December 2010, 19:08

      advertising

        
       

  3. #3
    Junior Member level 1
    Points: 1,681, Level: 9

    Join Date
    Dec 2004
    Posts
    18
    Helped
    0 / 0
    Points
    1,681
    Level
    9

    Re: Vertical PNP ERC error in Calibre:"NWELL Regions should be tied to POWER"

    Thank you very much for your reply erikl!

    It is a relief that you also considered this as a dummy error message! I hope the boss does too!
    As for your suggestion it was surely to the right direction. However, I searched in all the rule files for the model, for the specific layers of the device and for NWell rules, but had no success on finding such an exception layer (though I found some exceptions regarding ESD devices).
    If I receive an official answer from IBM I will keep you informed.

    Thank you again,
    mix



    •   Alt30th December 2010, 17:01

      advertising

        
       

  4. #4
    Advanced Member level 5
    Points: 35,610, Level: 46

    Join Date
    Mar 2008
    Location
    USA
    Posts
    5,717
    Helped
    1657 / 1657
    Points
    35,610
    Level
    46

    Re: Vertical PNP ERC error in Calibre:"NWELL Regions should be tied to POWER"

    I have seen some process kits where there is another metal
    layer used for power routing, which ends up Boolean'd to the
    same layer as signal but is checked additionally (like MET1 and
    PMET1). POWER is not a normal net name but probably in the
    extract deck there is some logic going on. Maybe you have to
    tag your layout net somehow. Go and grep the rules decks
    (if they are unencrypted) for 'POWER' and follow the yellow
    brick road.



--[[ ]]--