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Power Analysis using Synopsys DC

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vivek_p

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Power Analysis Synopsys

Can anybody explain the step by step procedure for finding the dynamic and leakage power of a design using Synopsys DC
 

report_power
The report have complete information
 

You can calculate leakage power by report_power command. But dynamic power calculation will unaccurately.
Dynamic power depends on work mode you use. For example if you are modeling some arithmetical operations result can be differ from that calculated in logical operation.
For more accurately measurement of dynamic power you should make following steps:
1. Get SDF file (for backend netlist it includes RSPF information)
2. simulate your netlist with SDF and to generate VCD file. Clock frequencies should be the same as in DC.
3. convert VCD to SAIF
4. read SAIF file and report_power
Usually, calculated value differs from calculated without VCD and simulation. And it have good correlation with chip.
 

You can calculate leakage power by report_power command. But dynamic power calculation will unaccurately.
Dynamic power depends on work mode you use. For example if you are modeling some arithmetical operations result can be differ from that calculated in logical operation.
For more accurately measurement of dynamic power you should make following steps:
1. Get SDF file (for backend netlist it includes RSPF information)
2. simulate your netlist with SDF and to generate VCD file. Clock frequencies should be the same as in DC.
3. convert VCD to SAIF
4. read SAIF file and report_power
Usually, calculated value differs from calculated without VCD and simulation. And it have good correlation with chip.

thank you!

I want to know how can I convert the VCD to SAIF, with which TOOL & CMD?

I was told that VCS can do it,.

But I just do the pre-sim & post-sim with VCS NCVerilog or Modelsim.

thank you again!
 

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