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When netlist is Power awared netlist(means netlist has vdd vss connection), then tool will use power awared library to find out the power consumption.
To perform power analysis better to use power theater tool by sequence.
Thanx
power aware netlist will have logical power connectivity.
Added after 3 minutes:
Vivek, The RTL (verilog) needs to be synthesized targeting a technology and then you can use those libraries, using some synopsys/sequence/apache tools to get vectorless power if you just provide the activity factor of the processor.
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