design compiler retiming questions

Hello,

I am new here and new to logic design. I am currently doing some project using Synopsys Design Compiler and have some questions about its retiming function. If you have help me, I would very appreciate. Thank you in advance.

The problem is very simple. I am synthesizing a 8*8 multiplier using "optimize_registers" command. But DC reports following warning:

Warning: The following registers are considered to be
'fixed' during retiming. They are end-points of timing exceptions
such as 'set_false_path'. (RTDC-34)
a8_reg[0] (DFFSSRX1)
a8_reg[1] (DFFSSRX1)
a8_reg[2] (DFFSSRX1)
......

In my verilog, I basically put 8 registers in series at the inputs. I don't know those registers can not be moved and why there are timing exceptions.

Here is my verilog code:

module mult (clk, rstN, a , b, c);
parameter DATA_WIDTH = 8;
input clk,rstN;
input [DATA_WIDTH-1:0] a, b;
output [2*DATA_WIDTH-1:0] c;

reg [DATA_WIDTH-1:0] a1,a2,a3,a4,b1,b2,b3,b4;
reg [DATA_WIDTH-1:0] a5,a6,a7,a8,b5,b6,b7,b8;

assign c = a8 * b8;

//synopsys sync_set_reset "rstN"
always@(posedge clk)
if (!rstN) begin
a1<=0; a2<=0;
b1<=0; b2<=0;
a3<=0; a4<=0;
b3<=0; b4<=0;
a5<=0; a6<=0;
b5<=0; b6<=0;
a7<=0; a8<=0;
b7<=0; b8<=0;
end
else begin
a1<=a; b1<=b;
a2<=a1; b2<=b1;
a3<=a2; b3<=b2;
a4<=a3; b4<=b3;
a5<=a4; b5<=b4;
a6<=a5; b6<=b5;
a7<=a6; b7<=b6;
a8<=a7; b8<=b7;
end
endmodule

I don't know why you will get this warning.
But if your want to check whether your retiming work or not, there are two methord:
1): set clock, to see the clock frequency different for retiminged design and not retiminged synthesis result.
2): use simulation to see the a0_reg[?] / a1_reg[?] ../b0_reg[?] / b1_reg[?] ... value in gate level simulation.

By the way: if you use retiming, you may get some problem in LEC check. So you would better partition the piple by hand, not through synthesis tool.

what commands are you executing on dc_shell prompt? in your constraints file you would find false_path which could be preventing dc ..

jaydip said:

what commands are you executing on dc_shell prompt? in your constraints file you would find false_path which could be preventing dc ..

Click to expand...

Happy New Year everybody

Following is my simple script. I indeed added max_delay constraints to the outputs and registers which I think is why DC reports false_path warning. But I don't add those max_delay constraints to the outputs and registers, DC treats those paths as unconstrained paths which is another part I feel confused. Thank you for spending timing looking into it.

# Define system clock period
set clk_period 1
set clk_name clk
create_clock -period $clk_period clk
set_drive 0 clk
set_clock_uncertainty -setup [expr 0.1*$clk_period] $clk_name
set_operating_conditions TYPICAL
set auto_wire_load_selection true

# Define design environment
set ALL_INS_EX_CLK [remove_from_collection [all_inputs] [get_ports clk]]
set max_cap [expr [load_of saed90nm_typ/AND2X1/IN1]*5 ]
set_driving_cell -lib_cell DFFX1 -pin Q $ALL_INS_EX_CLK
set_drive 0 {clk rstN}

set_load $max_cap [all_outputs]

# Define design constraints
set_max_area 0

#set_input_delay $clk_q_plus_inv -clock $clk_name [all_inputs]
set_input_delay 0.08 -clock $clk_name [all_inputs]
set_output_delay 0.05 -clock $clk_name [all_outputs]

set max_delay $clk_period

set_max_delay $max_delay -to [all_outputs]
set_max_delay $max_delay -to [all_registers -data_pins]

compile -map_effort medium

create_clock clk -period 0.5

optimize_registers -sync_trans multiclass

Added after 5 minutes:

yx.yang said:

I don't know why you will get this warning.
But if your want to check whether your retiming work or not, there are two methord:
1): set clock, to see the clock frequency different for retiminged design and not retiminged synthesis result.
2): use simulation to see the a0_reg[?] / a1_reg[?] ../b0_reg[?] / b1_reg[?] ... value in gate level simulation.

By the way: if you use retiming, you may get some problem in LEC check. So you would better partition the piple by hand, not through synthesis tool.

Click to expand...

I checked the design, because of the "false_path" constraints warnings, no retiming happened. But I indeed tried to use DC pipeline command to explicitly tell DC to partition the design into 3 stages, this works very well. But I just want to figure out why I cannot use optimize_registers and insert Regs at the inputs. The script is list above.

if you read command description for optimize_register command, it clearly tells that in presence of set_max_delay (and some more commands) retiming will be limited and infct sometimes it may worsen the timing .. reason behind this restriction also seems quite logical to me ..

u do one thing, remove max_delay constraints from ur script .. as that constraint any how looks to me as redundant for you design .. define input, output delay instead nd try ...

all the best ..

Yeah, you are right. I can use the set_input/output delay constraints to replace the set_max delay constraints to avoid the timing exceptions warnings. Thanks for your help. I really appreciate.