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Looking for HV ESD Pad

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marcelo.baru

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hv esd

1) Pad type: I/O Resistor-less HV analog pad. Also looking for HV power pads for Vdd and Vss.
2) Pad size: The pad sizes shall be less 92 um X 92 um.
3) Pad ring: I have both 3.3V and 15V rings in IO section, but they are
separeted. The sizes for the pad ring is less than 92 um X 65 um each for Vdd and
Vss.
4) Total pad size: Less than 92 um X 235 um.
5) ESD requirement: Large than 6 kV.
6) Operating frequency: low frequency application.
7) Power consumption of the pads: During operation, the analog pad should consume no power.
8) Fabrication process: TSMC 0.35u 3.3V/15V 2P4M Polycide process.

Anyone experienced in this design or has something off-the-shelf that fits these requirements?

Thanks,
Marcelo
 

esd for hv power ics

we have 12V tolerable pads in our design, and can resist 2000V HBM stress, not as high as your design, the key element we used in our design is:
1. SCR device (silicon controlled rectifier) shorted to vss.
2. special diode string to vss, turned on by an RC timer.
 

hv esd design

We have recently worked on this same process node for HV application. I will check if I can link you directly to the IP provider that has these cells available including silicon proof.

Some further questions:
- Does the IO need Overvoltage/undervoltage tolerant support? --> Then a local protection clamp is required. Otherwise it may be possible to rely on 'dual diode' approach for the IO

- Total ESD area = 92um x 235um > 21.000 um2. This area is available for 1 power clamp between Vdd and Vss and some ESD protection from IO to Vdd /Vss. Correct?

- The leakage must be '0'. Is order of magnitude nA OK? Is this similar for the leakage at the power cell?

Good luck!
 

Thanks guys. ESDSolutions: I would appreciate if you can link me to the IP Provider. I will get back to you with the answers to your questions.

Thanks,
Marcelo
 

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