What should be the value of load signal in this parallel to serial converter code?

Hello

I need help in the following parallel to serial converter.. what's the value of load should be ?? shall it be like a clock ?? cause in all cases i tried the output is only the last bit in the shift register .. or is there something wrong with the code ???


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity pts2 is
Port (clk : in STD_LOGIC;
parallel_in : in STD_LOGIC_VECTOR (7 downto 0);
load : in STD_LOGIC;
serial_out : out STD_LOGIC);
end pts2;

architecture Behavioral of pts2 is

signal reg :std_logic_vector (7 downto 0);


begin


process(clk)

begin

if (clk'event and clk='1')then

if (load ='1') then
reg <=parallel;
else
reg<= reg (6 downto 0)&'0';
end if;

end if;

end process;

serial_out <= reg(7);

end behavioral;

Added after 3 hours 14 minutes:

I really need a very simple code.. cause i dunno how shall i assign the load signal !!!

Parallel to Serial

Hi

Once the transfer is completed , u should set ur load =0, so then only next 8 bits will be given, else the other device will think that the converter is still busy. because

for getting the 8 inputs , it takes only one clock cycle. But for sending serially it takes 8 clock cycles.

Consider ur design. In the above case u have only one 8 bit array to store the first set of inputs. In the second clock cycle, the converter outputs the LSB and in the same clock cycle, it receives second set of inputs. But u have only one array . So it over writes that array and all ur first set of inputs will be erased...

This problem can be solved as by making the load as inout. Once the seriall conversion is completed, clear the load signal. Then the device will think that the converter is ready for the next set of inputs.

So in ur design u change the load as inout. Clear after the serial transmission is completed

If there is any wrong please correct me. If this is helpful ..........don't forget to click on helped me

Thanks and Regards
Deepak

Re: Parallel to Serial

In the second clock cycle, the converter outputs the LSB and in the same clock cycle, it receives second set of inputs. But u have only one array . So it over writes that array and all ur first set of inputs will be erased...

Click to expand...

You probably didn't understand, how the design (a really simple one) works.

The serial shift out actually starts after deasserting the load input. There is nothing erased or similar. In a typical design, load would be active during one clock cycle. It isn't a clock, but a kind of clock qualifier. And it's required to keep timing constraints (setup and hold time) related to clk input.

So in ur design u change the load as inout

Click to expand...

That's completely wrong. You can't set a signal from two sources, either by using inout or any other means. Just try!

If you want evaluate the rising edge of load, this can be done by registering it in the clk process and comparing present and previous state.

Re: Parallel to Serial

hey the code for parellel to serial convertor is given in the book
digital design by
zwolinsky
on pg no 182 approximately....
enjoy