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Simulated and measured gain are not same .......for folded cascode opamp ..why???????

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ASHUTOSH RANE

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hello friends
I am designing folded cascode opamp,
i have got simulated Opamp gain of 6kv/v but the tool shows measured gain of 80v/v only....what can be wrong in set up or tool or What is wrong in anything

NOTE: "simulated Gain" is calculated by taking gm and Rout obtained from tool after simulation for each transistor,
"measured gain" is obtained with signal of 100uv and 50Khz signal @ CM level of 1 volt
 

Either you have made mistakes in your hand calculations or your testbench is wrong.
Show us the equation that you used for calculating Rout of folded-cascode OTA and in addition the schematic of the testbench you use for small-signal (ac) analysis.
 
If the amp is one stage, and designed in mos process, the gain is less than 100. So the test result is right.
 
Problem 1 - modeling dudes are lazy liars. Tattoo that on the inside of your left
eyelid.

Your Rout had better be the parallel 1/gDS value of all transistors attached to
the gain node, and this (gDS) is often a poor fit especially at short channel,
when operating at the transition from linear to saturated, etc. This latter is
kind of inherently where your folded cascode amp will be operating.
to
 
xihuwang said:
If the amp is one stage, and designed in mos process, the gain is less than 100. So the test result is right.
Click to expand...

Thanks for your reply xihuwang,
i m designing single stage folded cascode in 180 nm CMOS process ........so how much gain can be expected from such a amplifier ??...i have already obtained near by 250 of maximum gain ....
 

Please check the circuits and make sure that the transistor is biased in the correct region. Increasing the length of transistor is helpful for the gain.
ASHUTOSH RANE said:
Thanks for your reply xihuwang,
i m designing single stage folded cascode in 180 nm CMOS process ........so how much gain can be expected from such a amplifier ??...i have already obtained near by 250 of maximum gain ....
Click to expand...
 
jimito13 said:
Either you have made mistakes in your hand calculations or your testbench is wrong.
Show us the equation that you used for calculating Rout of folded-cascode OTA and in addition the schematic of the testbench you use for small-signal (ac) analysis.
Click to expand...

I HAVE USED THE FORMULAS GIVEN IN RAZAVI'S BOOK SO THAT SHOULD NOT GIVE ME DIFFERENCE MORE THAN 20-30%
also my all transistors are in saturation.....can u tell me how much Vds should be more than Vth (Vgs-Vth) and Vdsat.
 

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