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Timing Related problem

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anubhaw

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I want to know that how to increase the frequency for a circuit i.e there given two flip flop and some combinational logic between them . let after calculating all the delay we get the maximum frequency be 100HZ .. so question is how we can increase the frequency without any change in combi logic or step and hold time or any delay......
 

You can change the the order of the combinational logic by writing the verilog code accordingly of you can seperate the combinational logic into chunks and insert f/f between them like a pipeline approach.
PS: the second one will cause increase in area and cost.
 

Skew the clock of the 2 F/F, which is the main idea of cycle borrowing.
 
thanks a lot.. i am looking into it...... :):)

ebuddy said:
Skew the clock of the 2 F/F, which is the main idea of cycle borrowing.
Click to expand...


---------- Post added at 12:38 ---------- Previous post was at 12:32 ----------

Thanks.. but can u elaborate the same...
ebuddy said:
Skew the clock of the 2 F/F, which is the main idea of cycle borrowing.
Click to expand...
 

Ok, let me try.

This is the original design:
DFF DFF1 (.clk(CLK), .d(D1), .q(Q1));
DFF DFF2 (.clk(CLK), .d(D2), .q(Q2));
D2 = f(Q1); // f is the combinational logic, and has delay of 10ns, for example;

After skew of clocks, the new design is:
CLK_skew = BUF (CLK);
DFF DFF1 (.clk(CLK), .d(D1), .q(Q1));
DFF DFF2 (.clk(CLK_skew), .d(D2), .q(Q2));
D2 = f(Q1); // f is the combinational logic, and has delay of 10ns, for example;

Between the old design and the new design, the only change is DFF2 clock line is delayed, comparing to DFF1's clock. Now if you plot the timing diagram and do some analysis, you should be able to reach the conclusion that you can increase the clock frequency and the circuit still works!
 

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