Regarding Design Compiler

design compiler setup clock

Hi all,

I am doing synthesis a particular module.
I give clock as over constrained. Then I applied critical range, grouping paths
set_flatten true -effort high
set compile_new_boolean_structure ture
set_structure -timing true
compile -map_effort high
report_constraint -all_violators
ungroup -all -flatten
set_false_path -from [get_ports nRst]
compile -incr -map_effort high

But it is still says violation. After ungrouping , violation is very much reduced.
If there is violation, I find the critical path of startpoint and endpoint.
Actually I read some pdf that to analyze the critical path.

What to do further? some cell name OAI22X4 is showing the value as high in timing report. Whether we can write the script to pick another cell.(i,e using dont touch).
I need to know how to solve critical path violation values.
Need help plz

ddc to db design compile r

Are you actually sure that the tool is not doing as good a job as it could?

Some regular structures are a challange for DC and are better done manually:
1. Parity XOR trees
2. Any arithmetic functions (if you own a DC ultra license try the command partition_dp to improve arithmetic timing).

Another thing you can try is to enable retiming (this has repercussions on formal verification later on though).

Is your wireload model very conservative? If yes, do a trial layout - problem might go away or you might be able to fix it by just using usefull clock skew.

critical range

Hi,

I need to know if we increase the DRC constraints
i,e (Max_fanout, max_transition, max_capacitance_

is there any chance to reduce setup violations? Why its reducing....
Few people stating that it wil lreduce hold violation ....

Any answers plz

write+out.db+design+compiler

Analyze below points wrto your design.

1) does the violations is more than 10-20% of the your clock. DCcant optimize if its more than 20-30%. Its optional with DC ultra license and depends on the arithemetic and combo logic in the design.
2) What is the critical range specified in the design(Generally 10% of the lowest clock period).
3. Make separate path group for the violating paths (like Inputs, outputs path groups and violating path groups). And apply strict critical range for violating path groups.
4. Dont try to fix hold as well as setup in same run(remove set_fix_hold command if you have)
5. check DC license, try to use 2006.06-SP3 or above. Algorithms are revised and atleast will give 5% of the resualts better.
6.　Are you trying with Auto WLM turn it on (by default)?. Default option will give slightly better results.
7. OAX...Cellsa are OR_AND logic gates. Even though it shows more timing value, its the best DC is doing instead of picking up OR gate as well as AND gate. Because you applied set_flatten command, it might take these type of cells.
8. If you are comfortable with Prime time, write out DDC/DB in DC and read the same in PT and try with Whal if analysis and write the script and use the same script for changes in DC.
9. Avoid using low drive strength cells in the intital runs.
10. Check for the high fanout cells /high transition nets in the critical paths.
11. Check the critical path , is this true path or False path?. If false path, you know what to do?.


Let me know if you have any issues.. By the way , what technology and whats the target frequency of your design?.

Regards,
Sam

design compiler write -format flatten

Hi Sam,
Thanks for ur valuable information.
No, My violation is not more than 15% of my clock period.
1) Here i specify my critical range as 3.0
2) I seperate violating path as group i.e
group_path -name pathsin -critical_range 3.0 -from [all_inputs ]
group_path -name pathsout -critical_range 3.0 -from [all_outputs]
report_net_fanout -high_fanout
group_path -name PCIX_clk -critical_range 3.0 -to PCIX_clk
Whether this is correct? Since my targetted freq is 66 MHZ. But i give over constraint i.e around 70 MHz.
3)Actually avoid using low drive strength cells means ? I dont know regarding this step.
4)After grouping , i applied constraint like
set_flatten true -effort high
set compile_new_boolean_structure ture
set_structure -timing true

compile -map_effort high -boundary_optimization
report_constraint -all_violators

ungroup -all -flatten
set_false_path -from [get_ports nRst]
compile -incr -map_effort high
report_constraint -all_violators

Now its showing setup violation of around -0.40 only for pathsout group..(i.e output port side)
How to reduce further setup violation

Thanks
DIN

design compiler, compile path group

hai energitic,
small mistake in your script in path group specification..

group_path -name pathsout -critical_range 3.0 -from [all_outputs]


It should be
group_path -name pathsout -critical_range 3.0 -to [all_outputs]

because , outputs are endpoints. There wont be any paths from output ports. All the paths end at output port. DC doesnt recognize this path group and its take it in the clock/register path group. so your critical range doesnt consider for this path group..Try modifying this. it may solve your problem.

Regarding low drive strengths ,In the library, cells with 0.5x,1x,2x,3x.....10x drive strength cells are avaialble. Low drive strength cells will consume more delay and it will create timing problems at initial stages. Initially try to put set_dont_use on these cells . After analyzing for final synthesis , you can remove this set_dont use in your script..


let me know any issues ..

Regards,
Sam

d0 cell drive strength delay timing

Hi
Thanks for finding my mistake..
Then one more thing, i need to clarify..
u mention that use low drive strength cells..

Point Incr Path
--------------------------------------------------------------------------
clock X_clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 12.80 12.80 r
nTrdy (inout) 0.00 12.80 r
U_PcixCore/U_Pcibusif/syn65/Y (NOR2X4) 0.04 12.84 f
U_PcixCore/U_Pcibusif/net274039/Y (NOR2X4)0.14 12.98 r
U_PcixCore/U5/Y (BUFX12) 0.18 13.15 r

U_Core/U_Mas/U157/Y (AOI211X2) 0.09 13.41 f
U_Core/U_Mas/U164/Y (MXI2X4) 0.18 13.59 r
U_Core/U_Mas/U349/Y (NAND2X4) 0.10 13.69 f
U_Core/U_Mas/U350/Y (OAI21X4) 0.17 13.86 r
U_Core/U_Mas/U360/Y (OAI21X4) 0.25 14.10 f
U_Core/U_Mas/U206/Y (NAND2X2) 0.38 14.48 r
U_Core/U_Mas/U152/Y (INVX3) 0.16 14.65 f
U_Core/U_Mas/U658/Y (NAND2X1) 0.16 14.81 r
U_Core/U_Mas/U839/Y (CLKINVX1) 0.14 14.95 f
U_Core/U_Mas/U713/Y (NOR3XL) 0.44 15.38 r
U_Core/U_Mas/U1000/Y (AOI33XL) 0.23 15.61 f
U_Core/U_Mas/bytecount_reg[10]/D (DFFRHQXL)

clock _clk (rise edge) 14.10 14.10
clock network delay (ideal) 1.00 15.10
clock uncertainty -0.50 14.60
U_Core/U_Mas/bytecount_reg[10]/CK (DFFRHQXL) 0.00 14.60 r
library setup time -0.14 14.46
data required time 14.46
--------------------------------------------------------------------------
data required time 14.46
data arrival time -15.61
--------------------------------------------------------------------------
slack (VIOLATED) -1.15


Here NAND2X2 is giving more delay value as 0.38, if i reduce that means my data arrival time will little bit low, so violation can reduce... Whether i can mention set_dont_use NAND2X2 so that it automatically take NAND2X4 since its delay is 0.10.... this is correct ?

Then one more thing OAI21X4 is using 2 places, but its value is different...
I dont know whether this is correct or not..

Since just now i learned DC and i am working.....
How to use set_dont_use on library cells ? plz let me know

set_dont use

1)You have clock window of 14.10ns and your input delay 12.80ns. So you have 1.30 ns . capture side , you have 1 ns network delay and 0.5 ns uncertinity. and negative lib setup time of 0.14ns. So you have 0.94 ns delay left for combo logic .
You need to make sure that your combo logic should optimize it for 0.94 ns if all the constraints you given are correct.

2)Then one more thing OAI21X4 is using 2 places, but its value is different...
I dont know whether this is correct or not..

It should be correct. The delay calculation engine depends the input slew and output load . In the same path, the cell might be used for different characterstics of the interpolation, so the cell delay might be different. so currently assume its correct and concentrate on other problem. will help you how to find delay later.

3 ) set_dont_use libname/Cell name
Ex; you have slow.lib as your lib name and nand2x1 need keep it as dont use,
set_dontuse slow.lib/nand2x1

4) To see the difference for diff cells used , you should try what if analysis. If you put dont use attribute on the cell, DC wont pick that cell for optimization. So analyze and apply dont use attribute. It doesnt mean, nand2x4 is having 0.10ns fixed delay. It varies depends on the input slew.

Regards,
Sam

slew optimization design compiler

Hi Sam,
Thanks.
Since i use set_max_area 200000.0
since i no need to optimize area side. I am concentrating only timing side.
If suppose i tell set_dont_use lib_cell/OAI21X1 ...
this is somewhat giving delay of 0.46 ... if i suppose in another place its showing 0.10 so it is not fixed delay as u mentioned before. Since it varies depend on input slew.
DC will try to take some other cells of the same kind,

how i come to know it will put less delay value only...
It may have very low drive strength know?

That situation what we can do? which cells we have to set dont use?

partition_dp

After analyzing your design and constraints, you need to put set_dont_use attribute on the cells. Experienced synthesis enginer /layout enginer can tell, which cells will trouble in meeting timing. For you, at beginer level, you need trails to find out ,which cells doesnt require for synthesis.

As i explanied, you cant find which cell will give less delay in critical path. The delay of the cell depends on input transition(slew),output load and drive strength of the cells and etc.. report_delay_calculation command in DC ,will tell you how tool will calculate delay for cell (From input to output). Check the man pages and understand it..