Questions related to Physical design: kindly help (part 1)

physical design questions

I dont want that few of my questions remain unanswered so I am splitting questions in several post, moderator please dont merge it :

Here are the questions:

1. how will we decide chip core area ?

2. how to do IR Drop analysis. what kind of infomations does it contain ?

3. what is configuration file ? what does it contains ? for what is it used

4 How to specify Core Utilization factor and Core IO margin? how u will decide this one..

5. what is Block halo?:

Re: Questions related to Physical design: kindly help (part

1.how will we decide chip core area ?

Die area = std. cell area (area of NAND gate * no. of std. cells) + macro area + 30% (for optimization)
Chip Area = Die area + (consideration for IO ring and core ring)

2. how to do IR Drop analysis. what kind of information does it contain ?

It depends on tool flow, which tool r u using. IR drop shows how much power is reaching to particular Cell.

3. what is configuration file ? what does it contains ? for what is it used
Don’t know, which configuration file r u talking abt.

4 How to specify Core Utilization factor and Core IO margin? how u will decide this one..
Normally as rule of thumb, we keep 70-75% utilization factor.
IO margin = 2* IO height + 2* Core ring spec (width of VDD and VSS ring)

5. what is Block halo?
Designer doesn’t want ant std cells to be placed very close to macro (Bcoz of DRC violation at routing stage). So designer puts placement blockage around the macro, that is HALO


Hopefully I have answered ur all question correctly

Re: Questions related to Physical design: kindly help (part

There are very good explanation .

Re: Questions related to Physical design: kindly help (part

halo around macro blocks are needed to avoid congestion around them during routing