Power clamp ESD ERC error

The Power clamp is shown here:


The LVS passed, the ERC shows error that " mos connected to both power and ground" .

The Mclamp transistor's drain and source should connect to vdd and vss respectively. How should I avoid this ERC error? Thanks.

The process is tsmc.

shanmei said:

The Power clamp is shown here:
View attachment 147556

The LVS passed, the ERC shows error that " mos connected to both power and ground" .

The Mclamp transistor's drain and source should connect to vdd and vss respectively. How should I avoid this ERC error? Thanks.

The process is tsmc.

Click to expand...

I guess, if clamp device covers the ESD_CLAMP Layer, this error will disappear. Please check once.

Cheers.
bsrin

You sometimes have to ignore well intentioned bad advice.

Might see if there's a configuration / options that can be
adjusted prior to running ERC.

Or, make the clamp device sit under a symbol which has
D, G, S, B pins and looks like a MOSFET, but is not one
that gets recognized as such; unless ERC runs hierarchically,
it will not "see" that below is a naughtily-connected
MOSFET.

In Cadence you could insert a trivial presistor and then
the MOSFET will not be seen as directly connected.
In fact, since you're trying to deal with amps of current
traveling long distances, some effort to represent the
bussing resistance is a good idea (I'd bet your clamp
will need to size up, if you put a few thousand squares
of worst case metal resistance in series). That's why
clamps are often made small and distributed about the
periphery, even more than one per corner.

You should add an explicit back-diode, MOSFET taps
can be allowed way too sparse to be useful as B-D
diodes in forward conduction.

Also, this FET should follow ESD design rules (which
might improve the body diode some, but check).

bsrin said:

I guess, if clamp device covers the ESD_CLAMP Layer, this error will disappear. Please check once.

Cheers.
bsrin

Click to expand...

Thanks. I think there should be a layer define the power clamp. However, I don't find the ESD_CLAMP layer. My process is tsmc180 1.8V process. Do you know there might be other layer to define? Thanks.

- - - Updated - - -

I added the SDI layer, it still has the issue.

- - - Updated - - -

- - - Updated - - -

dick_freebird said:

In Cadence you could insert a trivial presistor and then
the MOSFET will not be seen as directly connected.

Click to expand...

I found that the there is no presistor layout from tsmc process. I add the presistor in schematic, but layout there is not. Then LVS can't pass. Thanks.

Are you passing all DRCs? Is there a special pcell you should be using?

The DRC is passed. Thanks.

You do not place presistors in layout, they are a schematic
"trick" to represent parasitic resistance without messing up
LVS (presistor netlists as resistor in schematic/Spectre, but
a short (nil) in layout extraction; if you want resistance to
be extracted, place a "resistor" polygon or series of rectangles
over the metal trace). Then you would have to place a
"M1resistor" (or whatever) from the schematic library to
make LVS match.