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[SOLVED] Ultra Low currents through MOS devices.

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nitishn5

nitishn5

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Is there any problem in using MOS devices biased to carry very small currents in the range of 0.25nA? For example a NMOS/PMOS mirror circuit mirroring 0.25nA.

The devices are long length but are still in sub-threshold.

I know that matching of the currents would be an issue and there could be leakage comparable to the actual current.

Is there any other fundamental issue I might be missing here?
 

Hi,

leakage currents in CMOS device mainly depend on temperature. Avoid chip temperature over 40°C.
Maybe you can amplify the current or you can us a peltier device to get constant temperautre.

Because even small capacitors may bring large error with these low currents you might consider active shielding of the lines.

Hope that helps

Klaus
 
I made current mirrors works with 125pA in 0.35um but I remember that leakage through substrate was countable. In cmos nodes > 0.5um is possible to operate with current in a range of 10pA (see de Gernonimo, O'Connor paper about baseline holder circuit from IEEE TNS 2000), but below 0.25 it's very hard - you need wery long, segmented transistors. And never trust to simulations if you are see e.g. "expected "drain current around 100pA but your gate-to-source voltage is near zero (much below the threshold).
 
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