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why disable timing check in gate level timing simulation?

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tariq786

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I have seen couple of posts on this forum as well as objectmix.com where people have suggested disabling timing check during gate level timing simulation.

https://www.edaboard.com/threads/47636/


My point is what is the use of gate level timing simulation, if you disable timing check?

It is true that with timing check ON, you get too many warnings or perhaps errors, but should n't those be noted and corrected rather than being ignored with no timing check?

Please educate me if i am missing some thing.

Thanks

kind regards,
tariq786
 

But I know that we are doing Two types of simulation.
With Time(after PD- with SDF) and Without time
and in without time : two types 1) With zero delay
2) With unit delay
 
You do not want to have timing checks enabled if your delay information is not accurate enough. Sometime you only get this information after place and route is complete.

Static timing analysis is far more accurate than dynamic simulation, so there's no need to enable timing checks in simulation if your static analysis tools are doing the checks for you.
 
Hi Dave,

I have placed and routed the design. Now i have correct delay information about gates as well as interconnects.

I am not relying on the static analysis tool. There has to be a reason for running gate-level timing simulation.

To me it makes sense to enable timing checks in the placed and routed design.

What do you think?
 

The timing check between synchronizers are not required to check during the GLS. how do we handle this?.
You need to add disable timing check in the GLS setup.
 

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