What is Super Pipline?

Hello Dears
Please explain a little about Super Pipline. what is the differences between super pipline and dynamic one or ordinary one? I didn't find any clear notes about it?
Thanks a lot
Mostafa

is a super pipeline a normal pipeline at a higher clock speed?>

sheikh said:

Hello Dears
Please explain a little about Super Pipline. what is the differences between super pipline and dynamic one or ordinary one? I didn't find any clear notes about it?
Thanks a lot
Mostafa

Click to expand...

It's either this...which (to me at least) is no different than 'pipelining', but maybe the authors thought that what they were doing was really 'super'.
https://en.wikibooks.org/wiki/Microprocessor_Design/Pipelined_Processors

Or perhaps you're referring to a 1983 action puzzle game released for the Commodore 64
https://en.wikipedia.org/wiki/Super_Pipeline

Kevin Jennings

Hi Dear J-K
plz accept my apologize. (I mean Pipeline )
Thanks for your first link, it was good.

- - - Updated - - -

Hi Dear TrickyDicky
sorry for late reply I didn't have access to net. yes it is. In fact I wanted to know about Pipeline applications in image processing and how to do it, but someone said that search for super_Pipeline and dynamic one.

sheikh said:

In fact I wanted to know about Pipeline applications in image processing and how to do it, but someone said that search for super_Pipeline and dynamic one.

Click to expand...

Pipelining is simply breaking up a 'long' computational task that you initially think can be completed in one clock cycle into several steps that take multiple clock cycles. Here the word 'long' means 'long time'.

As a an example, let's say you need to compute the following function:
a <= b + c + d + e when rising_edge(clock);

But when you do this, the synthesized implementation takes 50 ns to complete and you have a 10 ns clock. In that situation, there will be several options, but one of them could be this:

bpc <= b+c when rising_edge(clock);
dpe <= d+e when rising_edge(clock);
a <= bpc+dpe when rising_edge(clock);

Let's say that now the clock can run at 10 ns, you've met your goal. You're still computing the same function, but the final result instead of coming out after one clock cycle instead it comes out after two clock cycles. You've pipelined the computation into smaller steps that can each run at a faster clock cycle so now the overall system can run at a faster clock speed.

There are tradeoffs involved that are not demonstrated by this example. Some considerations are:
- You've now delayed 'a' by a clock cycle, so whoever receives 'a' might need to know about this extra delay
- Can the receiver of 'a' tolerate an extra clock cycle of latency without modification?
- If the receive of 'a' cannot tolerate an extra clock cycle of latency without modification, then how extensive of a change is required in order to be able to tolerate the latency? If the change is extensive, then maybe there is a better way to reduce the delay (in this case, maybe a better algorithm?).

Kevin Jennings

Thanks Dear Kevin
useful as like as the first one.