What is the tracelength for USB3.0 Super Speed differential lines in PS-GTR?

[kakiitek]

Hi,
Would like some information on the topic above. The ug583 does not have any such information. Xilink forum is not accessible.
In addition, what would happen if the tracelength is exceeded? Is there any way to reduce the transmission speed?
Many thanks.
Best rgds,
KAKIITEK

 

[FvM]

The question isn't specific to Xilinx devices, refer to PCB guidelines for USB 3.0 and other 5 GBPS interfaces. A rule of thumb says max. 20 inch, reduce by 2 inch for each signal via.

 

[kakiitek]

Hi FvM, would be great if there is any documentation that says about the 20 inch critical tracelength. So far, different suppliers has a range of different critical length. Unfortunately, the Xilink Ultrascale+ does not provide any. What we would like to know is just how far we could route the SuperSpeed lines from the Ultrascale+ when the routing impedance is matched at 90 Ohm

Thanks!