Executing a script with design compiler and encountering error

hi

I have written this vhdl code and a script for it when i excute this scipt with design compiler i get this errors
but befor writing the scrpit i have Synthetized it with xilinx ISE there wasn't any errors!
what should i do can anone help me

Thanks in advance
----------------
errors:

Error: ./second.vhd:1: Syntax error at or near token '--'. (VER-294)
Error: ./second.vhd:64: The construct ''0' is not supported in this language. (VER-720)
Error: ./second.vhd:67: The construct ''1' is not supported in this language.
-------------------------
my vhdl code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;



entity project1 is
Port ( data_in : in STD_LOGIC_VECTOR (31 downto 0);
output : out STD_LOGIC_VECTOR (32 downto 0)

);
end project1;

architecture Behavioral of project1 is
type d_array is array (0 to 32) of std_logic_vector(31 downto 0);
type t_array is array (0 to 32) of std_logic_vector(31 downto 0);


CONSTANT data_array : d_array :=(x"00000000",x"0000ffff",x"00000300",x"00000600",
x"01fd0000",x"0180c000",x"0000003b",x"01fee000",x"01fd4000",x"00000001",x"00010000",
x"00000002",x"00000700",x"000002a1",x"025d8cc0",x"0000001f",x"ffffffff",x"13131313",
x"12121212",x"ffff0000",x"14141414",x"00000004",x"15151515",x"1f1f1f1f",x"18181818",x"13131212",
x"02000000",x"14131313",x"13131314",x"00000200",x"14141313",x"13131312",x"13121212");

CONSTANT tag_array: t_array:=(x"00000000",x"00000001",x"00000002",x"00000004",x"00000008",x"00000010",x"00000020",x"00000040",
x"00000080",x"00000100",x"00000200",x"00000400",x"00000800",x"00001000",x"00002000",x"00004000",x"00008000",x"00010000",

x"00020000",x"00040000",x"00080000",x"00100000",x"00200000",x"00400000",x"00800000",x"01000000",x"02000000",x"04000000",
x"08000000",x"10000000",x"20000000",x"40000000",x"80000000");


begin


process(data_in)
begin
for i in 0 to 32 LOOP

if ( data_in=data_array(i)) THEN


output <= '0'& tag_array (i); else


output<= '1' & data_in ;



end if;
end loop;
end process;



end Behavioral;
------------------------------
and my script:

set my_files second.vhd
set my_toplevel project1
set my_clock_pin CLK
set my_clk_freq_MHz 100
set my_input_delay_ns 0
set my_output_delay_ns 0
set link_library ./osu025_stdcells.db
set target_library ./osu025_stdcells.db
define_design_lib WORK -path ./WORK
set compile_ultra true
analyze -f verilog $my_files
elaborate $my_toplevel
current_design $my_toplevel
link
uniquify
set my_period [expr 1000 / $my_clk_freq_MHz]
set find_clock [ find port [list $my_clock_pin] ]
if { $find_clock !=

• } {
  set clk_name $my_clock_pin
  create_clock -period $my_period $clk_name
  } else {
  set clk_name vclk
  create_clock -period $my_period -name $clk_name
  }
  set_driving_cell -lib_cell INVX8 [all_inputs]
  set_input_delay $my_input_delay_ns [all_inputs]
  set_output_delay $my_output_delay_ns [all_outputs]
  compile -ungroup_all -map_effort medium
  compile -incremental_mapping -map_effort medium
  check_design
  report_timing
  report_timing -delay min
  report_timing -delay max
  report_timing -delay max > max_tim.rpt
  report_timing -delay min > min_tim.rpt
  
  write -f ddc -o ./Reports/myddc.ddc
  write -f verilog -o ./Reports/netlist_verilog.v
  write -f vhdl -o ./Reports/netlist_vhdl.vhdl
  write_sdf ./Reports/Stndrd_Dly_Frmt.sdf
  write_parasitics -o ./Reports/C_R_delays.spef
  write_sdc ./Reports/sdc.sdc

All these errors clearly indicate that these are version errors. Moreover, sometimes while copying the scripts from internet it is very important to use some common sense.

In your script you have written:
analyze -f verilog $my_files

first of all have you mentioned this variable anywhere? in your script? well i cant find it. moreover your code seems to be a vhdl code. then how can you specify "verilog" with analyze command.

Well, the command should be "analyze -format vhdl abcd.vhd

try this and check what all you have written in the script.. understand it then go for the run.. dont do anything blindly.

Cheers

thank u vijay.mani884 in fact i don't know how to write a script for dc to estimate power and critical path delay