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Re: how to use pll imbedded in FPGA ? similar questions for
Sorry, i try to make my question clearer. Firstly , i want to know is there a pll or a ADC imbedded in FPGA( I just kown the existence of plls). Secondly , i want to know how to use them ( because i don't need external monolithic...
I select the ss corner library as the default target library. Obviously, it results in the lowest work frequency after dc synthesisi. I wonder this gate level result will unconditionally pass the ff corner timing constrains ? how to verify the robustness under all corner ?
What is the difference on the effect against ESD between reverse biased base-epi junction and base-emitter short connected npn transistor ? One is diode , one is npn transistor. I guess the base emitter short connected npn is somewhat like ggnMOS. who can give an explicit distinguishing...
esd pre post
ok , here are more detailed infos: it is a bipolar process, Pin 2 is connected to substrate , the voltage of pin 1 is always lower than pin 2 (i.e. substrate voltage is not the lowest voltage of the chip). Below is the main part of the circuit between pin 1 and pin 2. I hope...
explain this picture
PIN 1 and PIN 2 are involved in this test, which pin is 2000v lower than the other?
It is important for determining the failure path.
0.9um seems a little bit thick than my evaluation. if 1.5um of the metal layer in bipolar process is reasonable, than 1 um wide metal can allow max 2mA current to flow through it. It also seems a little bit small.
Can someone tell the approximate value of the thickness of the metal layers in 0.25/0.18um process? I want to make a comparison between it and that in 2um bipolar process to evaluate the maximum current density that the metal can tolerate.
In a bipoalr process, i always find a N doped area( also can be called N tank) under the bondpad although they are not electrically connected. Who can explain the intention of doing so.
I want bulid a resistor in terms of a subcircuit in cadence composer. I expect the HSPCIE output netlist contains such lines " xAAA nodea nodeb mdname w=wi
L=li M=mi " . I will define a model for the mdname in other files. How can i realize it ?
Best regards!
Re: how to write a behaviour level voltage source in spectr
Thank you!
I want to express my more clrealy. Does pvcvs represent polynomial VCVS ?
If i want a time related sinusoidal wave which can be writtn as
EXXX nodea nodeb volt="sin(2*3.14159*Fosc*TIME+...
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