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corner selection during dc synthesis

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zhonghan

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I select the ss corner library as the default target library. Obviously, it results in the lowest work frequency after dc synthesisi. I wonder this gate level result will unconditionally pass the ff corner timing constrains ? how to verify the robustness under all corner ?
 

shelby

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In general, yes. Once you implement the clock tree there may be new violations that come up in the fast corner due to skew, but this is after the synthesis stage. Also, for designs in 65nm and below, you may want to check the temperature you are using at your slow corner. Temperature inversion effects can come into play that make timing worse at your slow cold corner.

You can always analyze your design in an STA tool using multiple corner analysis to confirm.
 

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