Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by yibai

  1. Y

    DC : combinational timing loop

    timing loop + rtl set_case_analysis command, it will make the clock domain as false path. them will be constrainted as different clock domain. Of coz the loop will be broken. and usually the mux 's timing we need not constraint it, because the mux's selection always tied to a constant in...
  2. Y

    Sorry for this kind of questions...

    none of them is key job in design house, maybe someday the job will be layoff...
  3. Y

    Denali question - verify reading mem operation, printInfo

    Denali question use denali's PLI , for detailed ,you can reference MMAV user guide.pdf.
  4. Y

    how to delay bus for about 2 or 3ns compared to the clock

    how to delay the bus? 1. rsim, just adding #DELAY 2. synthesis, set_output_delay -max for setup -min for hold.
  5. Y

    questions about Delay Chain

    yes, but it's cell delay larger than NAND and Inverter. it seems no way to satisify me. en. what your std cell delay of smic or tsmc 110 ns process. or 90 ns... mine: for example NAND2X1 about 0.03ns cell rising and falling
  6. Y

    Qusetion about DDR frequencies

    Re: Qusetion about DDR 1. right. 2. maybe. JEDEC wants to say it DQ , it's DQ.
  7. Y

    questions about Delay Chain

    what "W/H" mean? INVERTER, NAND, BUFFER are the fast cells. but Inverter pair has large initial delay, because of mux. NAND pair has large step delay... i need a new structure... Added after 34 seconds: oh, RC of coz can do that ,but i need digital method...
  8. Y

    questions about Delay Chain

    as we know, Turnable Delay Chain has initial delay , and pricision of delay step. i want to know, except inverter pair, buffer. there are other method to improve the delay chain's intial delay and step pricision? 3ks.
  9. Y

    how can I design SPI slaver by verilog

    there are many methods to sync the data. i think you must have another clock to do async interface. so: 1. FIFO 2. just internal Clock to SYNC all the signals. 3. spi clock latch the data, and then do async. ...
  10. Y

    How to find unconstrained paths in a design?

    report_analysis_coverage constant please use report_analysis_coverage to report the reason!
  11. Y

    Qusetion about DDR frequencies

    Re: Qusetion about DDR DDR400 of coz can run DDR266, DDR333. Because of the DDR SDRAM's DLL, the DLL's delay chain just can lock above 100Mhz Clock. so if the DLL cannot lock the input clock, it will fail. but i just can tell you that there is method to let ddr running on 60 Mhz.
  12. Y

    Does Latency is more important or Skew is more important?

    Re: Does Latency is more important or Skew is more important in fact, we hope latency and skew are both smaller. if we need run higher frenquency, the skew is more important. but, lantency more, we cannot balance the skew, the skew maybe more.
  13. Y

    How to delay a clock signal having a period T by T/4 ?

    Re: Delaying the Clock it let me remember the DDR/DDR2/DDR3 's DLL, 1/4 T delay for PVT .
  14. Y

    Comparison of ASIC with FPGA

    ASIC VS FPGA thanks
  15. Y

    Comparison of ASIC with FPGA

    My boss told me to use FPGA instead of ASIC.And the ASIC has designed for some years ago. I don't know it is right or not what my boss talk to me
See more

Part and Inventory Search

Back
Top