how to delay bus for about 2 or 3ns compared to the clock

[iamanderson]

how to delay the bus?

In my design, I have a problem, because of the hold time requiement, I have to
delay the Address bus for about 2 or 3ns compared to the clock, can anyone give
me some suggestion about this problem? I dont think it's a good idea to delay the
bus? but I have no good idea?
thanks
anderson

 

[yibai]

how to delay the bus?

1. rsim, just adding #DELAY
2. synthesis, set_output_delay -max for setup -min for hold.

 

[phildog]

Re: how to delay the bus?

#DELAY 3e-9
-max
-min

Freq at range 2kHz~1MHz.

 

[iamanderson]

Re: how to delay the bus?

thanks for your kind
the question is that if i add delay, I need to add for every bit of the Address bus
I use the delay cell in the lib, when I do synthesis, I use don't touch command for
these delay cells,but I don't think is a good idea,any other good choice?
thanks[/quote]

the following picture, clk is aligned with Address, the hold requirement is 0.5ns
so I decided to delay the Address to Address1, which meet my need.

 

[xigu2]

how to delay the bus?

if the address bus is too big to add delay cells,
you can turn the relative clock timing path.
short the clock tree, add big clk buf ...

 

[vlsichipdesigner]

Re: how to delay the bus?

hi,

my 2 cents,

* Make the clock early to the addressregisters, that way you can save in adding more buffers. If you dont want to disturb clock path, then the option is to use delay cells to delay the data path.

happy designing.

Chip design made easy
https://www.vlsichipdesign.com

 

[lik]

how to delay the bus?

Why not try add DLL to the address-bus clock?
In that case,you may improve both clock frequency and signal integrity.

 

[hzhou]

how to delay the bus?

You may use useful skew of clock network.

 

[pra]

how to delay the bus?

I think if you just add a buffer to the Address bus which delays the address bus by 1-2ns is enuf for you.

In RTL use a custom buffer and set don't remove on that. synthesis will not consider those u will have the delay u wanted after the clock too..

(OR)
if your address is an flopped out then increase the clk2q delay of that flop it will take care of this issue

Touching the clock tree is little bit dangerous than data path.

 

[syncom]

how to delay the bus?

May the re-synthesis and add set_input_delay -min 2ns
to solve it ?