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Hi,
I am trying to read in UPF at RTL level.
For the all standard Cells, Memories, Analog Macros - Power config file is used to add search path and db file name.
I have the below two observations -
1- After adding power config file, I have removed the corresponding RTL files of standard...
Thanks Shalin.
The below update has been done in SGDC, it helped in shift violations but not in capture violations.
Still I am getting violations in Capture - "Reset/Set to XXX flops is not controlled in Capture Mode"
Reset Scheme is as below -
IO --> PAD --> Scan Mux --> Flop...
Hi u24c02,
You can add Clock Gating Cell in the Top Level or inside the individual blocks as well. It is better to add CG cells at the Top.
You said your Clock Gating Cells are being removed in the synthesis, check whether you have connected the Clock Gating Cell output properly or not
Hi ,
YOu should try as below
module counter ( .....
...
...
input INC2;
output [2:0] COUNT;
reg [2:0] COUNT;
...
...
< Better to synchronized INCO0 in 'clk' domain before using in this module>>
CG_CELL_INSTNACE U_CG_CELL_INSTANCE_1
(
.clk(clk),
.en(INC0),
.se(dft_scan_enable),
.out(ck0)
)
...
Hi all,
I have faced with a very basic problem in vhdl instantiation.
There is signal called A_SL of type std_logic_vector(7 downto 0);
I want to connect it to another port of other module called B_USL of type std_ulogic_vector( 7 downto 0);
When I declare an intermediate signal call...
The address is coming from the processor. Cannot generate csn along with address.
we are also in Fix .. because we have that single cycle access constraint. Already that path is on critical path.
HI RCA,
My case is like - same address, data, mask bits driving into 4 cuts of memories. The chip select of the memories will be selected based on address.
My concern is that, when any cut is selected -still the address, data, mask bits of other 3 memories will be toggling. I want to reduce...
HI all,
I want to gate the Address, Data bus of the Memory when not selected from controlled.
what is the best possible ways to do it without adding more area on the address and data bus?
Hi all,
I need to generate chip select signal for memory through address decoding. It will be combo logic only and the read/write access has to be performed in single cycle.
As Chip Select is transparent to Memory Address, whenever memory address is changing the csn is toggling in between...
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