Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[ Memory Interface gated when not selected]

Status
Not open for further replies.

whizkid123

Junior Member level 2
Joined
Oct 6, 2011
Messages
23
Helped
1
Reputation
2
Reaction score
3
Trophy points
1,283
Location
Singapore
Activity points
1,421
HI all,

I want to gate the Address, Data bus of the Memory when not selected from controlled.
what is the best possible ways to do it without adding more area on the address and data bus?
 

If there are a direct connection between the processor and the memories, and only the chip select is gated, I don't really see without knowledge of your design, how you could gated address-data.. without additional logic.

Keep in mind, that you will have some buffers added along these nets during the placement-optimisation and hold time, so the mux/gate elements could be used to drive instead the buffers, so the additional area is not as much you could report after synthesis.
 

HI RCA,

My case is like - same address, data, mask bits driving into 4 cuts of memories. The chip select of the memories will be selected based on address.
My concern is that, when any cut is selected -still the address, data, mask bits of other 3 memories will be toggling. I want to reduce that activity.

THanks
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top