[Glitch Free Memory Chip Select Signal]

[whizkid123]

Hi all,

I need to generate chip select signal for memory through address decoding. It will be combo logic only and the read/write access has to be performed in single cycle.

As Chip Select is transparent to Memory Address, whenever memory address is changing the csn is toggling in between the clock period also.
I want to remove that extra toggling on memory address lines when memory is not selected.

Any suggestions please ?

Thanks
Murali

 

[rca]

Add a latch on the CSN path, transparent when you do a read/write otherwise blocked.
I don't really like latch, perhap you could flop the csn, really dependant of your timing access protocol.

 

[whizkid123]

Add a latch on the CSN path, transparent when you do a read/write otherwise blocked.
I don't really like latch, perhap you could flop the csn, really dependant of your timing access protocol.

Thanks rca .

Flop in my case not acceptable due to single cycle access constraint to the memory.
latch also cannot.
Any other suggestions Please.

 

[Analog Ground]

Do you have enough setup time and control of the clock duty cycle to latch the CS signal on the opposite (unused) clock edge? Or, can you delay the clock and then apply the decoder output to a D flip flip clocked with the delayed clock?

What technology are you using for the decoding? FPGA? PLD? Discrete logic? Custom IC?

 

[whizkid123]

Hi,

I cannot use the other side of the clock which makes the STA timing to meet twice the operating freq.
we are targetting for CustomIC.

Thanks

 

[rca]

The flop to save the CSN could be generated in the same time as the address generation, not at memory level, but at the bus level.

Dependand of the address mapping usage, you could used the MSB bit has direct chip select.
RAM0:0x1xxxYYYY
RAM1:0x2xxxYYYY
RAM2:0x4xxxYYYY
A single bit MSB is used for the CS, and the 16bits-LSB for address.

 

[whizkid123]

The address is coming from the processor. Cannot generate csn along with address.
we are also in Fix .. because we have that single cycle access constraint. Already that path is on critical path.

 

[rca]

The memory mapping is done by the designer not by the processor, you could arange the address mapping to map what I proposed before, no?