[SOLVED] [ Connecting std_logic_vector to std_ulogic_vector port]

[whizkid123]

Hi all,

I have faced with a very basic problem in vhdl instantiation.

There is signal called A_SL of type std_logic_vector(7 downto 0);
I want to connect it to another port of other module called B_USL of type std_ulogic_vector( 7 downto 0);


When I declare an intermediate signal call "C_signal_SL" of type std_logic_vector(7 downto 0). I am getting error for std_ulogic_Vector connection.
If I declare the internal signal as std_ulogic_vector .. I am getting an error for std_logc_vector port connection.

Please help me to solve this. Got stuck with this.

Thanks

 

[ads-ee]

It should be one of the following depending on which way you need to convert.
to_stdlogicvector or to_stdulogicvector

 

[whizkid123]

Hi,

Thanks
Let me try and get back to you.

 

[whizkid123]

Hi ads-ee,

It worked for me. However it works only for input ports and for output ports tool is throwing error.
My problem solved .

Thanks