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Recent content by venkatramanan

  1. V

    regarding rectilinear floorplan

    what precausions take for while doin rectilinear floorplan? what are the problems arises in notch area?
  2. V

    DRC error in 45 nm in calibre

    there are some new DRC rules added in 45nm and below technolgy.so interviewer asked this question to me.. " did u face any type of new DRC error and rules in ur project"
  3. V

    DRC error in 45 nm in calibre

    any one face new type of DRC error and rules in 45nm technology... help me ....
  4. V

    regarding clock specification file in SOC encounter

    what is meant by leaf pin ,through pin , exclude pin in .ctstch file...how we ll use?when we ll use? ple help me...
  5. V

    regarding source synchronous design

    what is meant source synchronous design and timing analysys?why we are using in physical design? wen we use and how to use ? help me ...
  6. V

    regarding typical timing analysys

    we are closing timing in best case and worst case...then why we goin for typical corner..?
  7. V

    regarding signal Electromigration

    how to do signal EM analysis in cadance SOC encounter tool.its possible ?
  8. V

    regarding instant count and gate count

    another one doubt .how clock gating violations occur...how to clear clock gating violatins in PNR
  9. V

    regarding instant count and gate count

    what is the differnce between inst count and gate count. for ex: 400k inst count means what is the gate count?
  10. V

    regarding module placement

    thank u :)
  11. V

    regarding module placement

    what is meant by module placements like fence, region, guide,.what is differnce between fence, region , guide.?
  12. V

    regarding clock gating violations

    clock gating pin violating setup and hold.so how we can clr that one
  13. V

    regarding clock gating violations

    what are the ways to fix clock gating violations?
  14. V

    regarding skew vs latency

    hi actually i search how uncertainty ll affect timing.so i got this details from vlsibank.com.i c't understand above statement.otherwise can u tell me any other reason is there.how clock uncertainity will affect timing after CTS
  15. V

    regarding skew vs latency

    hi, i c't understand following details.ple any one explin me how its affect timing.? Both clock skew and clock latency affect the setup time and hold time of a register in a similar manner. A clock skew of say 500ps means: - The clock transitions from 0 to 1 at time 0 - The clock...
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