Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

regarding clock gating violations

Not open for further replies.
Change the gating circuit to a known working design.

Which way of clock gating are you using? latch free or latched one?
Generally in latch free clock gating we get violations because of unnecessary changes in enable within a clock cycle.
So recommendation is to use latched clock which latches enable for entire clock period.
If you are already using latched clock than check if enable stable during rising/falling edge(to avoid setting/hold time violations)
refer the image shown below:

is it necessary to get warnings in check timing report if AND gate is used as a clock gating element?

but yes i am getting CLOCK GATING HOLD CHECK FOR THE INPUT PIN... But warnings? is it necessary?

Not open for further replies.

Part and Inventory Search

Welcome to