regarding clock gating violations

[venkatramanan]

what are the ways to fix clock gating violations?

 

[FvM]

Change the gating circuit to a known working design.

 

[venkatramanan]

clock gating pin violating setup and hold.so how we can clr that one

 

[babaduredi]

Which way of clock gating are you using? latch free or latched one?
Generally in latch free clock gating we get violations because of unnecessary changes in enable within a clock cycle.
So recommendation is to use latched clock which latches enable for entire clock period.
If you are already using latched clock than check if enable stable during rising/falling edge(to avoid setting/hold time violations)
refer the image shown below:

 

[rashmidesai]

hi
is it necessary to get warnings in check timing report if AND gate is used as a clock gating element?

but yes i am getting CLOCK GATING HOLD CHECK FOR THE INPUT PIN... But warnings? is it necessary?