venkatramanan
Member level 4
hi,
i c't understand following details.ple any one explin me how its affect timing.?
Both clock skew and clock latency affect the setup time and hold time of a register in a similar manner.
A clock skew of say 500ps means:
- The clock transitions from 0 to 1 at time 0
- The clock waveform would show a ramp starting from 0v at time = 0 to VDD at time = 500ps
- Assume that the register registers a data when the clock voltage = vdd/2.
- For this clock, the data would be registered in only at time = 250ps.
A clock latency of say 250ps means:
- The clock transitions from 0 to 1 at time 250ps
- The clock waveform would show a step at 250 ps.
- Assume that the register registers a data when the clock voltage = vdd/2.
- For this clock, the data would be registered in only at time = 250ps.
Setup for the regiser increases by 250ps. ( Logic delay of 250ps more can be put on the Data before the reg)
Hold for the register decreases by 250ps. ( Atleast 250ps of logic must exist between this register and the one previous to it if the data driven from the previous reg is to be registered into this reg ONLY IN THE NEXT CYCLE).
i c't understand following details.ple any one explin me how its affect timing.?
Both clock skew and clock latency affect the setup time and hold time of a register in a similar manner.
A clock skew of say 500ps means:
- The clock transitions from 0 to 1 at time 0
- The clock waveform would show a ramp starting from 0v at time = 0 to VDD at time = 500ps
- Assume that the register registers a data when the clock voltage = vdd/2.
- For this clock, the data would be registered in only at time = 250ps.
A clock latency of say 250ps means:
- The clock transitions from 0 to 1 at time 250ps
- The clock waveform would show a step at 250 ps.
- Assume that the register registers a data when the clock voltage = vdd/2.
- For this clock, the data would be registered in only at time = 250ps.
Setup for the regiser increases by 250ps. ( Logic delay of 250ps more can be put on the Data before the reg)
Hold for the register decreases by 250ps. ( Atleast 250ps of logic must exist between this register and the one previous to it if the data driven from the previous reg is to be registered into this reg ONLY IN THE NEXT CYCLE).
