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Recent content by urakiki

  1. U

    Re-target the technology

    Well, you never know the when they are really happen. The RTL is missing for some of the reason, and only left the final netlist. Of course I can write script to convert the netlist to the targeted library, it maybe cause some errors and messy which will be my last stand. By the way, is...
  2. U

    Re-target the technology

    In Synopsys DC, If I am not wrong, there a way, but Cadence RC I cant find how. I only can access the RC. LEC we still can verify with netlist vs netlist but load with both library.
  3. U

    size difference between design vison and encounter

    There are many aspects to cause the size different, both tools are running with different optimization method, this is normal to have size different but not more than 20% different btw both. I only can guess the constraints in both could be different, e.g in synthesis you have use WLM, (top...
  4. U

    Re-target the technology

    I have a synthesize netlist target to one foundry, now I need to change to other process, I don't have the RTL to re-synthesis again, can I revert back to the generic netlist or target to other process node directly. FYI I only can access Cadence RC.
  5. U

    Regression test (.asm) on the operation of the 8051

    Hi, I am evaluate a 8051. Does anyone know any website provide a regression test (.asm) on the operation of the 8051 Thanks
  6. U

    Question about the behaviour of an I2C which is acting as a master

    Re: i2c master behaviour Hi, It depend on the designer requirement. You can have I2C master retransmit slave address like 4/8 times, if still not ACK from the slave side, master should be send STOP.
  7. U

    Looking for SPI flash controller in HDL

    Re: SPI flash controller go to www.opencores.org
  8. U

    Interfacing Xilinx Coregen generated RAM with AHB interface

    Hi, I use xilinx coregen to generate ram. Can I interface this ram with AHB interface. If no what modification should i do? Thanks KIKI
  9. U

    VHDL code for implementing the infrared

    pulse repetition frequency vhdl sorry for lack info. I wish to design a IR receiver with APB interface. It may support RC5 or NEC format.
  10. U

    VHDL code for implementing the infrared

    Hi everybody, Could anybody provide me with a VHDL code implementing the infrared.
  11. U

    Timing loop detected warning in a synthesis report

    Hi All, I found the warning about the timing loop detecteds in my synthesis report. What is this warning mean? Is this a critical warning? How to solve it? Can someone explain some theory on the timing loop issue. thanks
  12. U

    Case error LOC when converting VHDL to Verilog

    Hi, I am new to VHDL. And I try to convert to verilog. -- signal internalCNT, CNTupto, internalCNTaddr: std_logic_vector(11 downto 0); type errorLOCtype is array (7 downto 0) of std_logic_vector(7 downto 0); signal errorLOC: errorLOCtype; ........ ........ ..... case...
  13. U

    Looking for info on flash memory controller

    Hi, anyone can share some info on the flash memory controller? Thanks
  14. U

    Looking for AMBA APB RTL

    Hi, ANyone have AMBA APB RTL. Thanks in advance
  15. U

    Looking for APB RTL

    Hi, Everyone have APB RTL?
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