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Interfacing Xilinx Coregen generated RAM with AHB interface

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urakiki

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Hi,

I use xilinx coregen to generate ram. Can I interface this ram with AHB interface. If no what modification should i do? Thanks

KIKI
 

AMBA AHB ram

u need to write a wrapper for ur ram to make ur module compatible with the ahb signals.
it may be a master or slave port depending on ur application.
if ur ram has to write out data to any peripheral then u have to write a master interface. if ur ram doesn't have to write out any data and only accepts data that is some peripheral writes to your module a slave port is sufficient.
refer the amba ahb manual for implementation.

**broken link removed**
page no 79 and 83.

regards
srinivas
 

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