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Re-target the technology

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urakiki

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I have a synthesize netlist target to one foundry, now I need to change to other process, I don't have the RTL to re-synthesis again, can I revert back to the generic netlist or target to other process node directly. FYI I only can access Cadence RC.
 

I pretty sure you already tried it, no?
Conceptually, I could imagine that should work, in reality I never do that, because how do you validate the synthesis with a LEC tool without the RTL?
 

I pretty sure you already tried it, no?
Conceptually, I could imagine that should work, in reality I never do that, because how do you validate the synthesis with a LEC tool without the RTL?

In Synopsys DC, If I am not wrong, there a way, but Cadence RC I cant find how. I only can access the RC.

LEC we still can verify with netlist vs netlist but load with both library.
 

Very interesting idea!
I have never though this before.
To verify the correctness, the way of "old netlist v.s. new netlist" can be applied.

By the way, I think that it's seldom to occur due to the following reason:
1. the RTL file is developed by the company itself or must be licensed by other IP provider.
2. even for the same company, the RTL must be updated for new version to remove bugs.

I try to search this key word on Solvnet but found fail.
The searching never stop.
 

Very interesting idea!
I have never though this before.
To verify the correctness, the way of "old netlist v.s. new netlist" can be applied.

By the way, I think that it's seldom to occur due to the following reason:
1. the RTL file is developed by the company itself or must be licensed by other IP provider.
2. even for the same company, the RTL must be updated for new version to remove bugs.

I try to search this key word on Solvnet but found fail.
The searching never stop.

Well, you never know the when they are really happen. The RTL is missing for some of the reason, and only left the final netlist.

Of course I can write script to convert the netlist to the targeted library, it maybe cause some errors and messy which will be my last stand.

By the way, is there any way to get back the generic format netlist using some other tools?
 

I don't know how are you going to accomplish this without the rtl. Even if you write a script it will turn messy as you have already admitted. You may also end up with a sub-optimal netlist. Further you will encounter problems in formal verification as well.
 

There is a way and i have done this myself using Cadence RC.

read old tech lib + new target tech lib
read_netlist (old tech), sdc , etc
mark all old tech lib cells as "set_dont_use"
synth -to_map -eff high -no_incr
synth -to_map -eff high -incr
write_hdl --> this you should have the netlist with new target lib

This is kind of psuedo netlist to netlist operation.
I do not approve of this flow as a substitute but it really helps in cases/ times when schedule is a concern or non-RTL availability. the disadvantage here is that you will not get a best structured netlist since you do not have the RTL and most transformations are already done in the netlist, but it will not be that bad.
 

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