Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by tongson

  1. T

    SPI-3 PHY layer implementation-- NEED help!

    You can get some reference on the opencores.org.
  2. T

    Synplify pro error "Reference to unknown variable glbl

    check the synplify pro's installation lib.
  3. T

    What should i do after assigning the Pin Package (Spartan3)?

    ABOUT FPGA? pls check the information below the main window.
  4. T

    Need help on component seclection !

    Try low-density FPGA do it.
  5. T

    how to implement the JK flipflop->edge control phase dete

    clk'event and clk = '1' j = 1; clk'event and clk = '0' k = 1;
  6. T

    How to read flash via fpga?

    Go to ipcore website and download the ip, then program your FPGA.
  7. T

    VHDL to Verilog Problem !

    u can use the software to translate it.
  8. T

    Confused by the post place&route simulation

    check your code, if a1---->a3 sequentially set cycle by cycle, it maybe behaviour simulation mismatch the P&R netlist. Try to modify the delay in the behavioral simulation. Good luck!
  9. T

    VHDL to Verilog Problem !!!

    You should re-simulate the code after you translated it, especially for timing information! it can not be synthesis!
  10. T

    Spartan2 output maximum current.

    please check the corresponding datasheet about themselves.
  11. T

    suggestion on IC front-end design

    I suggest u should learn about hardware knowledge, and think about the principle about circuit working. Good Luck!!!
  12. T

    Which simulation tool is better, VCS 7.0 or NC-Verilog 5.4 ?

    VCS7.0 VS. NC-Verilog5.4 Nc-verilog is easy to use!!! VCS is not be controlled easily! The speed of them is almost same.
  13. T

    NCELAB error: rts_seghandler - SIGSEGV unexpected violation

    ncelab SIGSEGV Firstly, you should check the result of compilation. Then ncelab your module one by one.
  14. T

    Problem with wrong bit order from a BCD dip switch

    Bit order? shift it and and oprator can help you.
  15. T

    Problem with using Simulate Behavioral Model in Modelsim

    Modelsim help You can continue to run the simulation using the "continue" toolbar. Try!!!
See more

Part and Inventory Search

Back
Top