VHDL to Verilog Problem !!!

[angjohn]

is there any way to write if(clk' event and clk='0') (which is in VHDL) into Verilog. other than writing negedge or posedge in the always@()!!!

 

[semiconductorman]

You don't need to do always @(negedge clk) ; all you need is
@ (negedge clk) ;

You use always where you would have used process in vhdl.

 

[angjohn]

thanks for the reply but i wan to do following thing which is in VHDL into Verilog:

process (clk)

if (clk'event and clk =1)
q<='1';

else q<='0';

end process;

can anyone tell me how to modified the above code into verilog, please !!!

 

[dr.farnsworth]

Hello angjohn,

Do u need a software which can convert vhdl file 2 verilog file ?
If so check this site ...

http://www.ocean-logic.com/downloads.htm

may be this helps

Regards,
Dr.farnsworth

 

[spauls]

use XHDL by X tek

 

[semiconductorman]

thanks for the reply but i wan to do following thing which is in VHDL into Verilog:

process (clk)

if (clk'event and clk =1)
q<='1';

else q<='0';

end process;

can anyone tell me how to modified the above code into verilog, please !!!

Well well well .... you understand that your code does not make any good sence ..don't you ... q just follows the clk !!!! process will execute every time clk changes that is once at positive edge and again at negative edge and positvie edge you want q to go high and at negative edge you want to q to go low ... this would end up in q just equal to clk .. but if you just want to know this is how it gets translated ... I HOPE THIS IS FOR SIMULATION ONLY !!!!

//////////////////////////////////////////
always @ (clk)
begin
if (clk)
q = 1;
else
q= 0 ;
end
////////////////////////////////////////////
Or you could do it as
///////////////////////////////////////////
always
begin
@(posedge clk);
q = 1 ;
@ (negedge clk);
q = 0 ;
end
//////////////////////////////////////////

 

[tongson]

You should re-simulate the code after you translated it, especially for timing information!

it can not be synthesis!