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So can I say with the use of guard ring, parasitics BJT will still exist.
However the guard ring/epi layer (and other latch up prevention solution) help to channel the high current to the guard ring, instead of substrate. This stops large current from building up in the parasitic BJT to...
Hello,
Read a lot about guard ring prevent latch up. How exactly does guard ring prevent latch up?
There are a lot of discussion here that point out that the guard ring breaks up the SCR cause by the parasitics NPN and PNP, but I dont understand how a guard ring do that. So I dont understand...
What is the difference between guard ring and substrate tie?
A PMOS sits in a nwell, so the body is n type, need to be connected to the highest potential. This nwell is known as substrate tie or guard ring?
It is said that PMOS need a n type guard ring, and NMOS need a p type guard ring. In...
Hello,
In Razavi's book, design of analog CMOS integrated circuit.
chapter 3, pg 56/57
Its about a cs stage (M1) with diode connected PMOS (M2). input is at cs stage. output is taken at the D of CS stage
its gain is given as gm1/gm2. i understand this part.
then it further shows that
1)gain =...
Hello
There are 3 gm equations that can be used
1/ gm=2Id/Vgs-Vth
2/ gm= sqrt(2k(W/L)Id)
3/ gm= k(W/L)(Vgs-Vth)
when do u know which equations to use to determine the gm?
Equation 1, if u have Id constant, gm will decrease with increasing vgs-vth. I can connect a common source with ideal...
hello,
How do we know which way is the correct connection?
here is my understanding why circuit B doesnt work. But i cannot put my head around why circuit A works.
in circuit B. Break loop at A and inject a signal. If A increase then causing M1 to go Low, giving more current in M0 and M2. The...
Hello,
How can I run corner with Ocean?
I saved a copy of ocean script to run paramateric analysis. How can I include corners to it.
Anyone can help me out?
Hello,
Native nmos has a lower Vth than NMOS. Looking at the layout both device have the same layers. How do we differentiate them in layout?
NMOS is formed from nwell in p-substrate. How about native nmos?
thanks
Hello all,
In razavi's design of analog CMOS integrated circuit, chapter 3, it states/shows that body effect decrease the output resistance.
But I find it puzzling. I bias the NMOS source with a certain voltage, eg 0.3V.
Setup 1: Base and Source are connected together to 0.3V bias. (No body...
Hello all,
the output resistance is given as
1) satuation region, R=1/(Lamda*Id).
2) linear region, R=1/[u.Cox.(w/l).(vgs-vth)]
In these cases, PMOS will have higher outout resistance as PMOS has lower mobility and Id. Is my understanding correct?
However in Razavi's design of analog CMOS...
Hello all,
I'm trying to find the open loop gain and 3dB cutoff frequency of a simple 2 stage amplifier.
I have break the circuit (in ac analysis) at 2 different location to see if there is any difference in ac response. Both circuit are break in high impedance point. AC analysis Fig1 and Fig2...
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