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a question in razavi book cs stage with diode connected MOS

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surreyian

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Hello,

In Razavi's book, design of analog CMOS integrated circuit.
chapter 3, pg 56/57

Its about a cs stage (M1) with diode connected PMOS (M2). input is at cs stage. output is taken at the D of CS stagecs stage with diode connected pmos.png
its gain is given as gm1/gm2. i understand this part.

then it further shows that
1)gain = VGS2-VTH2/VGS1-VTH1
gain will be large if u set M1 overdrive small and M2 overdrive big.

and there is another equation
2) gain= (k(w/l)(vgs1-vth1))/((k(w/l)(vgs2-vth2))

this equation shows opposite trends. how can I explain this?
i'm a bit confused about which equation to use.

the current through the circuit is the same. with changing W/L. increase vin, increase the overdrive of cs stage, cause vout to go low, which also increase the overdrive of M2(diode connect PMOS). how can we increase the overdrive of one MOS and not the others?

i will be grateful if someone can go through this with me.
 

Junus2012

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Hi
dont be confused and take it like this

Av=gm1*1/gm2.......(1)

for the saturation region (which is the condition of the MOS amplifier circuits) gm = K'(W/L).(Vgs-Vth).......(2)

since vgs-vth=Overdrive voltage(Von) (at the edge of the saturation region).... Von=(2Id/K'.W/L)power0.5..........(3)

put 3 in 2 you get gm = (2.Id.(W/L).K')Power0.5...........(4)

now put 4 in 1 you get av= (W/L)1/(W/L)2 so the gain is not affected by the current but only with the transistor ratios :)

have fun
 

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