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guard ring vs substrate tie, are they the same thing?

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Feb 10, 2006
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What is the difference between guard ring and substrate tie?

A PMOS sits in a nwell, so the body is n type, need to be connected to the highest potential. This nwell is known as substrate tie or guard ring?

It is said that PMOS need a n type guard ring, and NMOS need a p type guard ring. In this case is the guard ring the substrate tie?

A P+ guard ring in a P- substrate is both a guard ring and
a substrate tie. Other permutations are not. A ring is a
tie, but a tie is unlikely to be a ring unless you declare it
has to be.

A PMOS sits in a nwell, so the body is n type, need to be connected to the highest potential. This nwell is known as substrate tie or guard ring?
IMHO substrate tie would be a confusing designation for a PMOS' body, better call it its body tie (or body tap). It's not a guard ring.

It is said that PMOS need a n type guard ring, and NMOS need a p type guard ring. In this case is the guard ring the substrate tie?
Better call such rings either a body (or n-well) tie (n+ type on n-well ring around a PMOS) or a substrate tie (p+ type on substrate ring around an NMOS in substrate).

Even if not absolutely necessary, it's not a bad idea to use ring-type substrate/body ties around noise-sensible or noise-generating and/or high current leading circuit parts. But these should not be designated as guard rings! Their purpose is to just guarantee the best possible connection between the transistor's source and its body in order to keep the body effect as small as possible. Never let the source current run over these body ties - always use separate connections to GND resp. VDD.

A guard ring has nothing to do with the transistor/circuit itself - it's always a separate structure. It's proper purpose is to screen a transistor or circuit from (or to) other nearby circuit elements by catching straying charge carriers and/or divert otherwise inpinging/escaping noise to GND resp. VDD. And it's usually an n+ on n guard ring (connected to VDD) around one or more NMOS transistor(s) on p-substrate, or a p+ on p guard ring (connected to GND) around an n-well containing one or more PMOS transistors.
This is an excellent question - because there is a lot of confusion in the industry regarding these terms and concepts.

Here is my understanding (I am not pretending that this is the only possible one and that it is 100% correct - it's just my understanding):

1. "Well tie"

A "well tie", or "body tie", or "substrate tie" - is a heavily doped (n+ or p+) regions of silicon (also known as - active, diffusion, od, diff, moat, etc.) sitting in a well or substrate of the same type conductivity, but doped at a lower level (for example - p+ in p-well, or n+ in n-well).
The purpose of the well tie is to supply a solid, well defined voltage to the well / substrate / body. (body is a region of well / substrate close to the body, or channel, of MOS transistor, and directly affecting its threshold voltage - Vt, and other characteristics.
In physical verification, a term "well tie" is reserved for an (artificial) via connecting active (diff) with the "well" ("substrate") (what's called "substrate" in physical verification is a whole other area of confusion and misunderstanding - and a subject for a separate discussion).

Without "well tie" (i.e. without n+ or p+ doped regions) there would be no Ohmic contact between metal interconnects and lower doped semiconductor. A physical contact area between the well tie and the metal contact (going from the lowest metal layer to silicon) is actually creating an Ohmic contact - so that the voltage in metal is equal to the "voltage" in semiconductor (I say "voltage" because a more correct term is "quasi-Fermi level/potential for majority carriers").

The problem is that even though there may be a well tie, providing a solid voltage to the well, the well potential may not be constant over the well area (wells can be huge in lateral dimensions - hundreds and thousands of microns), due to various current flow effects, and - a very high resistivity of the wells (of the order of - very roughly - 10 kOhm/square, for sheet resistance). To keep the potential of a large area well constant, the well ties should be placed as densely as possible over the well area, and very often they are placed around the well periphery, forming a ring shape. Well tie may be a small square (for one contact), or a rectangle filled with the contacts, or a ring field with contacts, or any other shape (filled with contacts).

A well tie will also repel minority carriers (i.e. carrier of opposite type) from entering the well (to be later collected by the heavily doped regions of the same type) - so it also plays the role of a guard ring.

2. "Guard ring"

A "guard ring" is a generic term describing some design/layout elements intended to block the flow of minority carriers from an injector (aggressor) to a collector (victim).
It can be formed by n+ or p+ implants (sitting in the wells of the same or opposite doping type), or wells (or deep wells), or deep trenches, or something else.
The idea is either to block the flow of minority carriers (by providing a physical or potential barrier to them), or to recombine them (and thus extract them through recombination).
Various life time killing mechanisms can be used (heavy doping of opposite polarity is one, special life-time killing implants - like inert gases, carbon, etc. -is another example).

A guard ring may have a shape of an actual ring, or any other shape (rectangle, L-shape, touching rings, etc.).

The rings can be intended to isolate an aggressor (injector) from affecting other (sensitive) parts of the chip, or to protect sensitive parts of the chip from external influence.

Guard rings can be "passive" or "active".
While well tie should (normally) be always connected to a solid voltage reference (like VSS/ground or VDD/power net), a guard ring may not be connected to a voltage reference, and left floating.

Guard rings are used to prevent "substrate coupling" (a very vague term, in my opinion) - i.e. various parasitic substrate effects caused by minority carriers:

1. latchup
2. minority carrier injection in power management circuits caused by inductive loads)

Very often, minority carrier and majority carrier effects (very different by their physics) are intermixed - because carriers can easily change from minority to majority type and vice versa by traversing doping regions of opposite type.

Another problems is that there is a lot of confusion in the industry regarding such concepts as "substrate noise" and "substrate coupling", very often - a lack of understanding of minority versus majority carrier effects, and - even good textbooks do not explain these things in deep enough detail.
(also - no entries in Wikipedia on guard rings!).

It would be really nice to come to a consistent set of definitions and explanations on ties, wells, guard rings, etc.

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