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Recent content by surajdash

  1. S

    Output of ADPLL using xilinx

    Can someone please tell me if the following output is a correct one for an ADPLL. I have this doubt because the output signal is not in phase with the input signal and its duty cycle is also not 50%.
  2. S

    Frequncy multiplier in verilog

    What if my system has only one input and I need to generate a clock using that signal. Like I need to generate the clock for the K counter and ID counter (DCO) which are multiples of the clock signal given as input.
  3. S

    Frequncy multiplier in verilog

    Actually I wanted to know how can i create another signal which has a frequency M times the input signal frequency where M>1. So that the signal generated has a frequency greater than that of the input frequency. ADPLL helps me get a signal which has a frequency lower than that of the input signal.
  4. S

    Frequncy multiplier in verilog

    Is it possible to create a frequency multiplier with verilog that can be implemented in a FPGA? That means given a input signal of frequency f can a circuit be made that calculates the frequency M*f ???
  5. S

    [SOLVED] Creating verilog from a schematic in xilinx

    Sir I have already written the code and tried. I just wanted to know how to write the testbench for a schematic file? We can normally write a testbench for a verilog file. But how do we do it for a schematic??
  6. S

    [SOLVED] Creating verilog from a schematic in xilinx

    Can you tell me how do i write a testbench for a schematic??
  7. S

    [SOLVED] Creating verilog from a schematic in xilinx

    Can this verilog file be used as a module in any other verilog code?? I have this question because I am designing an ADPLL and I have designed the ID Counter in schematics but I have the rest of the code in verilog that works fine. So can I simply paste this verilog code ??
  8. S

    [SOLVED] Creating verilog from a schematic in xilinx

    How can we create a verilog file from an already created schematics file in xilinx.
  9. S

    [SOLVED] Verilog output viewing

    Thanks a lot vipinlal.
  10. S

    [SOLVED] Verilog output viewing

    Xilinx 12.3
  11. S

    [SOLVED] Verilog output viewing

    Can someone tell me how do i see waveforms of signals that are neither inputs or outputs of a verilog code but are used in the program in the modules.
  12. S

    [SOLVED] what is wrong with this code?? (Verilog)

    Thanks for your suggestion FvM I'll try to implement the code using case structure now. And about using blocking assignments I can use non-blocking assignments too. And yes you got it right `low and `high in place of binary 1'b0 and 1'b1. It was simply because it is my first verilog code and...
  13. S

    [SOLVED] what is wrong with this code?? (Verilog)

    Re: what is wrong with this code?? guys.. thank you all for ur responses.. i hv changed my code now... hopefully this works .. hv some odr parts to cmplete too.. this one yet goes like this... always @(posedge idclk) begin if(!carry) c_check = `low; if(!borrow) b_check = `low; if (delay)...
  14. S

    [SOLVED] what is wrong with this code?? (Verilog)

    Re: what is wrong with this code?? okay.. so the delay created by # xx is only for simulations?? it wont be synthesized but will it work nice for simulations.. i mean by seeing the result in xilinx after running the program by a testbench??
  15. S

    [SOLVED] what is wrong with this code?? (Verilog)

    Re: what is wrong with this code?? okay can someone plz help me ... i just need to know how to create a delay that can be synthesized and not not ignored for synthesis...
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