[SOLVED] Creating verilog from a schematic in xilinx

[skewed_clock]

How can we create a verilog file from an already created schematics file in xilinx.

 

[ckshivaram]

You should be able to get the Verilog from a schematic design in ISE. The file name should be the same name as the schematic file with ".vf"

You should find this file in your project directory, but you need to make sure your preferred language for the project is Verilog. Otherwise it'll make a .VHF; which is VHDL.

the .VF and .VHF files only exist if synthesis has been run on the schematic at least once. These files are a side-product of the synthesis process so they'll only be present if you've run synthesis at least once (they are removed as part of Cleanup Project Files).

 

[skewed_clock]

Can this verilog file be used as a module in any other verilog code??

I have this question because I am designing an ADPLL and I have designed the ID Counter in schematics but I have the rest of the code in verilog that works fine.
So can I simply paste this verilog code ??

 

[ckshivaram]

cant guarantee that in every case... you could try it better....

 

[skewed_clock]

Can you tell me how do i write a testbench for a schematic??

 

[ckshivaram]

this could give you an idea
http://www2.ece.ohio-state.edu/~bibyk/ece822/CHWangQualReport.pdf

---------- Post added at 20:28 ---------- Previous post was at 20:25 ----------

or try this
**broken link removed**

 

[skewed_clock]

Sir I have already written the code and tried. I just wanted to know how to write the testbench for a schematic file? We can normally write a testbench for a verilog file. But how do we do it for a schematic??

 

[ckshivaram]

I have not done those things but
did you see this
**broken link removed**
VHDL Tutorial: Learn by Example