Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Output of ADPLL using xilinx

Status
Not open for further replies.

surajdash

Junior Member level 2
Joined
Jun 21, 2011
Messages
22
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,440
Can someone please tell me if the following output is a correct one for an ADPLL. I have this doubt because the output signal is not in phase with the input signal and its duty cycle is also not 50%.

 

yadog

Member level 1
Joined
Mar 12, 2006
Messages
33
Helped
3
Reputation
6
Reaction score
3
Trophy points
1,288
Activity points
1,427
need more information about your design!
 

ajayboddhuna

Newbie level 3
Joined
Mar 13, 2013
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,297
hey surajdas ,can you please send ur adpll code to this mail (ajay.boddhuna@gmail.com) ..plz
 

AdvaRes

Advanced Member level 4
Joined
Feb 14, 2008
Messages
1,166
Helped
113
Reputation
220
Reaction score
50
Trophy points
1,328
Location
At home
Activity points
7,444
Hi,
Strange output. It seems like if you have missed an inverter somewhere (in the PFD or the CP).
 

mrflibble

Advanced Member level 5
Joined
Apr 19, 2010
Messages
2,724
Helped
679
Reputation
1,360
Reaction score
651
Trophy points
1,393
Activity points
19,551
Heh, the OP is from 2011. And Mr one-post-never-to-be-seen-again (well 2 post) is just looking for some code in the hopes to avoid some work. :p

And just to make sure I am interpreting that post correctly I checked his other post. Yup, domyworkplzkthxbye style.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top