Output of ADPLL using xilinx

[surajdash]

Can someone please tell me if the following output is a correct one for an ADPLL. I have this doubt because the output signal is not in phase with the input signal and its duty cycle is also not 50%.

 

[yadog]

need more information about your design!

 

[ajayboddhuna]

hey surajdas ,can you please send ur adpll code to this mail (ajay.boddhuna@gmail.com) ..plz

 

[AdvaRes]

Hi,
Strange output. It seems like if you have missed an inverter somewhere (in the PFD or the CP).

 

[mrflibble]

Heh, the OP is from 2011. And Mr one-post-never-to-be-seen-again (well 2 post) is just looking for some code in the hopes to avoid some work.

And just to make sure I am interpreting that post correctly I checked his other post. Yup, domyworkplzkthxbye style.