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Frequncy multiplier in verilog

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Junior Member level 2
Jun 21, 2011
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Is it possible to create a frequency multiplier with verilog that can be implemented in a FPGA? That means given a input signal of frequency f can a circuit be made that calculates the frequency M*f ???

Either as a time-discrete ADPLL, you know about it, or using built-in hardware PLLs available with some FPGA families.

Actually I wanted to know how can i create another signal which has a frequency M times the input signal frequency where M>1. So that the signal generated has a frequency greater than that of the input frequency. ADPLL helps me get a signal which has a frequency lower than that of the input signal.

ADPLL helps me get a signal which has a frequency lower than that of the input signal.
ADPLL can achieve frequency multiplication with an additional high frequency system clock.

What if my system has only one input and I need to generate a clock using that signal. Like I need to generate the clock for the K counter and ID counter (DCO) which are multiples of the clock signal given as input.

As said, you need a high frequency input clock or a FPGA with internal hardware PLL to generate it.

Making use of DLLs may help for your problem. Have the same signal passed through Delay loops to achieve a higher frequency for the input. I have not synthesized one, but have seen the concept of this in Xilinx.

You could use Digital Clock Managers (DCMs) which are provided by FPGA Vendor.

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